利用0.35μm工艺条件实现了性能优良的小尺寸全耗尽的器件硅绝缘体技术(SOI)互补金属氧化物半导体(FD SOI CMOS)器件,器件制作采用双多晶硅栅工艺、低掺杂浓度源/漏(LDD)结构以及突起的源漏区。这种结构的器件防止漏的击穿,减小短沟道效...利用0.35μm工艺条件实现了性能优良的小尺寸全耗尽的器件硅绝缘体技术(SOI)互补金属氧化物半导体(FD SOI CMOS)器件,器件制作采用双多晶硅栅工艺、低掺杂浓度源/漏(LDD)结构以及突起的源漏区。这种结构的器件防止漏的击穿,减小短沟道效应(SCE)和漏感应势垒降低效应(DIBL);突起的源漏区增加了源漏区的厚度并减小源漏区的串联电阻,增强了器件的电流驱动能力。设计了101级环形振荡器电路,并对该电路进行测试与分析。根据在3V工作电压下环形振荡器电路的振荡波形图,计算出其单级门延迟时间为45ps,远小于体硅CMOS的单级门延迟时间。展开更多
An analytical model for the channel potential and the threshold voltage of the short channel dual-material-gate lightly doped drain （DMG-LDD） metal-oxide-semiconductor field-effect transistor （MOSFET） is presented...An analytical model for the channel potential and the threshold voltage of the short channel dual-material-gate lightly doped drain （DMG-LDD） metal-oxide-semiconductor field-effect transistor （MOSFET） is presented using the parabolic approximation method. The proposed model takes into account the effects of the LDD region length, the LDD region doping, the lengths of the gate materials and their respective work functions, along with all the major geometrical parameters of the MOSFET. The impact of the LDD region length, the LDD region doping, and the channel length on the channel potential is studied in detail. Furthermore, the threshold voltage of the device is calculated using the minimum middle channel potential, and the result obtained is compared with the DMG MOSFET threshold voltage to show the improvement in the threshold voltage roll-off. It is shown that the DMG-LDD MOSFET structure alleviates the problem of short channel effects （SCEs） and the drain induced barrier lowering （DIBL） more efficiently. The proposed model is verified by comparing the theoretical results with the simulated data obtained by using the commercially available ATLASTM 2D device simulator.展开更多
Accounting for the deep Gaussian and tail exponential distribution of the density of states, a physical approximation for potentials of amorphous silicon thin-film transistors using a symmetric dual gate （sDG a-Si：H...Accounting for the deep Gaussian and tail exponential distribution of the density of states, a physical approximation for potentials of amorphous silicon thin-film transistors using a symmetric dual gate （sDG a-Si：H TFT） has been presented. The proposed scheme provides a complete solution of the potentials at the surface and center of the layer without solving any transcendental equations. A channel current model incorporating features of gate voltage-dependent mobility and coupling factor is derived. We show the parameters required for accurately describing the current-voltage （l-V） characteristics of DG a-Si：H TFT and just how sensitively these parameters affect TFT current. Particularly, the parameters＇ dependence on the I-V characteristics with respect to the density of deep state and channel thickness has been investigated in detail. The resulting scheme and model are successively verified through comparison with numerical simulations as well as the available experimental data.展开更多
For the first time,a simple and accurate two-dimensional analytical model for the surface potential variation along the channel in fully depleted dual-material gate strained-Si-on-insulator（DMG SSOI） MOSFETs is deve...For the first time,a simple and accurate two-dimensional analytical model for the surface potential variation along the channel in fully depleted dual-material gate strained-Si-on-insulator（DMG SSOI） MOSFETs is developed.We investigate the improved short channel effect（SCE）,hot carrier effect（HCE）,drain-induced barrier-lowering（DIBL） and carrier transport efficiency for the novel structure MOSFET.The analytical model takes into account the effects of different metal gate lengths,work functions,the drain bias and Ge mole fraction in the relaxed SiGe buffer.The surface potential in the channel region exhibits a step potential,which can suppress SCE,HCE and DIBL.Also,strained-Si and SOI structure can improve the carrier transport efficiency,with strained-Si being particularly effective.Further, the threshold voltage model correctly predicts a＂rollup＂in threshold voltage with decreasing channel length ratios or Ge mole fraction in the relaxed SiGe buffer.The validity of the two-dimensional analytical model is verified using numerical simulations.展开更多
文摘利用0.35μm工艺条件实现了性能优良的小尺寸全耗尽的器件硅绝缘体技术(SOI)互补金属氧化物半导体(FD SOI CMOS)器件,器件制作采用双多晶硅栅工艺、低掺杂浓度源/漏(LDD)结构以及突起的源漏区。这种结构的器件防止漏的击穿,减小短沟道效应(SCE)和漏感应势垒降低效应(DIBL);突起的源漏区增加了源漏区的厚度并减小源漏区的串联电阻,增强了器件的电流驱动能力。设计了101级环形振荡器电路,并对该电路进行测试与分析。根据在3V工作电压下环形振荡器电路的振荡波形图,计算出其单级门延迟时间为45ps,远小于体硅CMOS的单级门延迟时间。
文摘An analytical model for the channel potential and the threshold voltage of the short channel dual-material-gate lightly doped drain （DMG-LDD） metal-oxide-semiconductor field-effect transistor （MOSFET） is presented using the parabolic approximation method. The proposed model takes into account the effects of the LDD region length, the LDD region doping, the lengths of the gate materials and their respective work functions, along with all the major geometrical parameters of the MOSFET. The impact of the LDD region length, the LDD region doping, and the channel length on the channel potential is studied in detail. Furthermore, the threshold voltage of the device is calculated using the minimum middle channel potential, and the result obtained is compared with the DMG MOSFET threshold voltage to show the improvement in the threshold voltage roll-off. It is shown that the DMG-LDD MOSFET structure alleviates the problem of short channel effects （SCEs） and the drain induced barrier lowering （DIBL） more efficiently. The proposed model is verified by comparing the theoretical results with the simulated data obtained by using the commercially available ATLASTM 2D device simulator.
基金supported by the National Natural Science Foundation of China(No.61274085)the Cadence Design System,Inc
文摘Accounting for the deep Gaussian and tail exponential distribution of the density of states, a physical approximation for potentials of amorphous silicon thin-film transistors using a symmetric dual gate （sDG a-Si：H TFT） has been presented. The proposed scheme provides a complete solution of the potentials at the surface and center of the layer without solving any transcendental equations. A channel current model incorporating features of gate voltage-dependent mobility and coupling factor is derived. We show the parameters required for accurately describing the current-voltage （l-V） characteristics of DG a-Si：H TFT and just how sensitively these parameters affect TFT current. Particularly, the parameters＇ dependence on the I-V characteristics with respect to the density of deep state and channel thickness has been investigated in detail. The resulting scheme and model are successively verified through comparison with numerical simulations as well as the available experimental data.
基金Project supported by the National Natural Science Foundation of China(Nos.60976068,60936005)the Cultivation Fund of the Key Scientific and Technical Innovation Project,Ministry of Education of China Program(No.708083)the Specialized Research Fund for the Doctoral Program of Higher Education,China(No.200807010010).
文摘For the first time,a simple and accurate two-dimensional analytical model for the surface potential variation along the channel in fully depleted dual-material gate strained-Si-on-insulator（DMG SSOI） MOSFETs is developed.We investigate the improved short channel effect（SCE）,hot carrier effect（HCE）,drain-induced barrier-lowering（DIBL） and carrier transport efficiency for the novel structure MOSFET.The analytical model takes into account the effects of different metal gate lengths,work functions,the drain bias and Ge mole fraction in the relaxed SiGe buffer.The surface potential in the channel region exhibits a step potential,which can suppress SCE,HCE and DIBL.Also,strained-Si and SOI structure can improve the carrier transport efficiency,with strained-Si being particularly effective.Further, the threshold voltage model correctly predicts a＂rollup＂in threshold voltage with decreasing channel length ratios or Ge mole fraction in the relaxed SiGe buffer.The validity of the two-dimensional analytical model is verified using numerical simulations.
