An Improved CFD-synthesis Method for Predicting Inlet Dynamic Distortion

This article presents an improved computational fluid dynamics （CFD）-synthesis method to predict dynamic distortion. A steady-state flow field is derived from a CFD solution, through which are acquired total pressure, density, turbulence kinetic energy and others in steady-state at an aerodynamic interface plane （AIP）. Back-propagation artificial neural network （BP ANN） is used to find out the relationship between the measured flight turbulence and the CFD-computed turbulence parameters. The dynamic pressure is obtained by incorporating CFD-found total steady-state pressure with fluctuating pressure. Finally, the dynamic distortion is predicted by means of the synthesized dynamic pressure. The fairly good agreement between the computed inlet surface pressure and the flight test data bears out the reliability of CFD solution used in this article. To validate the proposed method, six sets of flight test data are used and the results show that the predicted dynamic distortion is well in line with the distortion displayed in flight tests. An examination of the traditional method is also accomplished and the comparison also shows that the proposed method is superior to the traditional one in higher consistency with flight test data.

Effects of distance between arc and heat sink on stress and distortion in DC-LSND welding technology

The characteristics of temperatures, stresses and strains fields have been studied numerically for a titanium alloy sheet welded with an improved gas tungsten arc welding method, in which a trailing spot heat sink is introduced to control the welding stress and distortion. The impinging jet model is employed to describe the internee heat transfer between the cooling media and the top suufuce of the workpiece. The influcnee of the distance between arc and heat sink is investigated. Results show that there is an ideal range of distance. Using the ideal distance, a low stress and no distortion welding structure can be derived.

A high-order model of rotating stall in axial compressors with inlet distortion

In this paper,a high-order distortion model is proposed for analyzing the rotating stall inception process induced by inlet distortion in axial compressors.A distortion-generating screen in the compressor inlet is considered.By assuming a quadratic function for the local flow total pressure-drop,the existing Mansoux model is extended to include the effects of static inlet distortion,and a new high-order distortion model is derived.To illustrate the effectiveness of the distortion model,numerical simulations are performed on an eighteenth-order model.It is demonstrated that long length-scale disturbances emerge out of the distorted background flow,and further induce the onset of rotating stall in advance.In addition,the circumferential non-uniform distribution and time evolution of the axial flow are also shown to be consistent with the existing features.It is thus shown that the high-order distortion model is capable of describing the transient behavior of stall inception and will contribute further to stall detection under inlet distortion.

High performance 14-bit pipelined redundant signed digit ADC

A novel architecture of a pipelined redundant-signed-digit analog to digital converter（RSD-ADC） is presented featuring a high signal to noise ratio（SNR）, spurious free dynamic range（SFDR） and signal to noise plus distortion（SNDR） with efficient background correction logic. The proposed ADC architecture shows high accuracy with a high speed circuit and efficient utilization of the hardware. This paper demonstrates the functionality of the digital correction logic of 14-bit pipelined ADC at each 1.5 bit/stage. This prototype of ADC architecture accounts for capacitor mismatch, comparator offset and finite Op-Amp gain error in the MDAC（residue amplification circuit）stages. With the proposed architecture of ADC, SNDR obtained is 85.89 d B, SNR is 85.9 d B and SFDR obtained is 102.8 d B at the sample rate of 100 MHz. This novel architecture of digital correction logic is transparent to the overall system, which is demonstrated by using 14-bit pipelined ADC. After a latency of 14 clocks, digital output will be available at every clock pulse. To describe the circuit behavior of the ADC, VHDL and MATLAB programs are used. The proposed architecture is also capable of reducing the digital hardware. Silicon area is also the complexity of the design.