Deep reinforcement learning based multi-level dynamic reconfiguration for urban distribution network:a cloud-edge collaboration architecture

With the construction of the power Internet of Things(IoT),communication between smart devices in urban distribution networks has been gradually moving towards high speed,high compatibility,and low latency,which provides reliable support for reconfiguration optimization in urban distribution networks.Thus,this study proposed a deep reinforcement learning based multi-level dynamic reconfiguration method for urban distribution networks in a cloud-edge collaboration architecture to obtain a real-time optimal multi-level dynamic reconfiguration solution.First,the multi-level dynamic reconfiguration method was discussed,which included feeder-,transformer-,and substation-levels.Subsequently,the multi-agent system was combined with the cloud-edge collaboration architecture to build a deep reinforcement learning model for multi-level dynamic reconfiguration in an urban distribution network.The cloud-edge collaboration architecture can effectively support the multi-agent system to conduct“centralized training and decentralized execution”operation modes and improve the learning efficiency of the model.Thereafter,for a multi-agent system,this study adopted a combination of offline and online learning to endow the model with the ability to realize automatic optimization and updation of the strategy.In the offline learning phase,a Q-learning-based multi-agent conservative Q-learning(MACQL)algorithm was proposed to stabilize the learning results and reduce the risk of the next online learning phase.In the online learning phase,a multi-agent deep deterministic policy gradient(MADDPG)algorithm based on policy gradients was proposed to explore the action space and update the experience pool.Finally,the effectiveness of the proposed method was verified through a simulation analysis of a real-world 445-node system.

Application of Global Dynamic Reconfiguration in Artificial Neural Network System based on Field Programmable Gate Array

Presented is a global dynamic reconfiguration design of an artificial neural network based on field programmable gate array(FPGA). Discussed are the dynamic reconfiguration principles and methods. Proposed is a global dynamic reconfiguration scheme using Xilinx FPGA and platform flash. Using the revision capabilities of Xilinx XCF32P platform flash, an artificial neural network based on Xilinx XC2V30P Virtex-Ⅱ can be reconfigured dynamically from back propagation(BP) learning algorithms to BP network testing algorithms. The experimental results indicate that the scheme is feasible, and that, using dynamic reconfiguration technology, FPGA resource utilization can be reduced remarkably.

Application of Remote FPGA Dynamic Reconfiguration System in LED Lighting

The dynamic reconfiguration technique based on field-programmable gate array （FPGA） can improve the resource utilization. Discussed are the dynamic reconfiguration principles and methods. Proposed is a remote dynamic reconfiguration scheme using Xilinx Virtex-Ⅱ FPGA and SMCS Ethernet Physical layer transceiver（PHY）. The hardware of the system is designed with Xilinx Virtex-U XC2V30P FPGA that embedds MicroBlaze and MAC IP core, and its network communication software based on transmission control protoeol/Internet protocol （TCP/IP） protocol is programmed by loading LwIP to MicroBlaze. The experimental results indicate that the remote FPGA dynamic reconfiguration system（RFDRS） can switch freely in the eight lighting modes of light emitting diodes （LED）, and that, using dynamic reconfiguration technology, FPGA resource utilization can be reduced remarkably, which is advantageous in the system upgrade and software update.

Multi-objective Dynamic Reconfiguration for Urban Distribution Network Considering Multi-level Switching Modes

The increasing integration of photovoltaic generators(PVGs) and the uneven economic development in different regions may cause the unbalanced spatial-temporal distribution of load demands in an urban distribution network(UDN). This may lead to undesired consequences, including PVG curtailment, load shedding, and equipment inefficiency, etc. Global dynamic reconfiguration provides a promising method to solve those challenges. However, the power flow transfer capabilities for different kinds of switches are diverse, and the willingness of distribution system operators(DSOs) to select them is also different. In this paper, we formulate a multi-objective dynamic reconfiguration optimization model suitable for multi-level switching modes to minimize the operation cost, load imbalance, and the PVG curtailment. The multi-level switching includes feeder-level switching, transformer-level switching, and substation-level switching. A novel load balancing index is devised to quantify the global load balancing degree at different levels. Then, a stochastic programming model based on selected scenarios is established to address the uncertainties of PVGs and loads. Afterward, the fuzzy c-means(FCMs) clustering is applied to divide the time periods of reconfiguration. Furthermore, the modified binary particle swarm optimization(BPSO)and Cplex solver are combined to solve the proposed mixed-integer second-order cone programming(MISOCP) model. Numerical results based on the 148-node and 297-node systems are obtained to validate the effectiveness of the proposed method.

Dynamic reconfiguration for TEG systems under heterogeneous temperature distribution via adaptive coordinated seeker

A thermoelectric generation(TEG)system has the weakness of relatively low thermoelectric conversion efficiency caused by heterogeneous temperature distribution(HgTD).Dynamic reconfiguration is an effective technique to improve its overall energy efficiency under HgTD.Nevertheless,numerous combinations of electrical switches make dynamic reconfiguration a complex combinatorial optimization problem.This paper aims to design a novel adaptive coordinated seeker(ACS)based on an optimal configuration strategy for large-scale TEG systems with series-paral-lel connected modules under HgTDs.To properly balance global exploration and local exploitation,ACS is based on'divide-and-conquer'parallel computing,which synthetically coordinates the local searching capability of tabu search(TS)and the global searching capability of a pelican optimization algorithm(POA)during iterations.In addition,an equivalent re-optimization strategy for a reconfiguration solution obtained by meta-heuristic algorithms(MhAs)is proposed to reduce redundant switching actions caused by the randomness of MhAs.Two case studies are carried out to assess the feasibility and superiority of AcS in comparison with the artificial bee colony algorithm,ant colony optimization,genetic algorithm,particle swarm optimization,simulated annealing algorithm,TS,and POA.Simulation results indicate that ACS can realize fast and stable dynamic reconfiguration of a TEG system under HgTDs.In addition,RTLAB platform-based hardware-in-the-loop experiments are carried out to further validate the hardware implemen-tation feasibility.

FSM deconposition VLSI architecture for dynamically reconfiguration

While some applications in memory can be constrained by memory bandwidth and memory cost, this paper proposes a transformation of the application into a one-bit FSM. When the finite state machine is very large, one way to improve the area and delay efficiently is to break down the large finite state machine into many smaller machines. The area efficiency can be improved if fewer machines are active simultaneously in the pipelined architecture. This can be achieved when using dynamic reconfiguration to map several sub machines onto the same hardware. This paper presents a methodology to break down the large finite state machine into many smaller machines and an architecture for the dynamically reconfiguration.

A Concept of Dynamically Reconfigurable Real-time Vision System for Autonomous Mobile Robotics

This paper describes specific constraints of vision systems that are dedicated to be embedded in mobile robots. If PC-based hardware architecture is convenient in this field because of its versatility, flexibility, performance, and cost, current real-time operating systems are not completely adapted to long processing with varying duration, and it is often necessary to oversize the system to guarantee fail-safe functioning. Also, interactions with other robotic tasks having more priority are difficult to handle. To answer this problem, we have developed a dynamically reconfigurable vision processing system, based on the innovative features of Cleopatre real-time applicative layer concerning scheduling and fault tolerance. This framework allows to define emergency and optional tasks to ensure a minimal quality of service for the other subsystems of the robot, while allowing to adapt dynamically vision processing chain to an exceptional overlasting vision process or processor overload. Thus, it allows a better cohabitation of several subsystems in a single hardware, and to develop less expensive but safe systems, as they will be designed for the regular case and not rare exceptional ones. Finally, it brings a new way to think and develop vision systems, with pairs of complementary operators.

Machine learning algorithm partially reconfigured on FPGA for an image edge detection system

Unmanned aerial vehicles(UAVs)have been widely used in military,medical,wireless communications,aerial surveillance,etc.One key topic involving UAVs is pose estimation in autonomous navigation.A standard procedure for this process is to combine inertial navigation system sensor information with the global navigation satellite system(GNSS)signal.However,some factors can interfere with the GNSS signal,such as ionospheric scintillation,jamming,or spoofing.One alternative method to avoid using the GNSS signal is to apply an image processing approach by matching UAV images with georeferenced images.But a high effort is required for image edge extraction.Here a support vector regression(SVR)model is proposed to reduce this computational load and processing time.The dynamic partial reconfiguration(DPR)of part of the SVR datapath is implemented to accelerate the process,reduce the area,and analyze its granularity by increasing the grain size of the reconfigurable region.Results show that the implementation in hardware is 68 times faster than that in software.This architecture with DPR also facilitates the low power consumption of 4 mW,leading to a reduction of 57%than that without DPR.This is also the lowest power consumption in current machine learning hardware implementations.Besides,the circuitry area is 41 times smaller.SVR with Gaussian kernel shows a success rate of 99.18%and minimum square error of 0.0146 for testing with the planning trajectory.This system is useful for adaptive applications where the user/designer can modify/reconfigure the hardware layout during its application,thus contributing to lower power consumption,smaller hardware area,and shorter execution time.

Dynamic Reconfigurable Structure with Rate Distortion Optimization

The Rate Distortion Optimization(RDO)algorithm in High Efficiency Video Coding(HEVC)has many iterations and a large number of calculations.In order to decrease the calculation time and meet the requirements of fast switching of RDO algorithms of different scales,an RDO dynamic reconfigurable structure is proposed.First,the Quantization Parameter(QP)and bit rate values were loaded through an H⁃tree Configurable Network(HCN),and the execution status of the array was detected in real time.When the switching request of the RDO algorithm was detected,the corresponding configuration information was delivered.This self⁃reconfiguration implementation method improved the flexibility and utilization of hardware.Experimental results show that when the control bit width was only increased by 31.25%,the designed configuration network could increase the number of controllable processing units by 32 times,and the execution cycle was 50%lower than the same type of design.Compared with previous RDO algorithm,the RDO algorithm implemented on the reconfigurable array based on the configuration network had an average operating frequency increase of 12.5%and an area reduction of 56.4%.

A Low-Area, Low-Power Dynamically Reconfigurable 64-Bit Media Signal Processing Adder

Multimedia devices like cellphones, radios, televisions, and computers require low-area and energy-efficient dynamically reconfigurable data paths to process the greedy computation algorithms for real-time audio/video signal and image processing. In this paper, a novel low-area, energy-efficient 64-bit dynamically reconfigurable adder is presented. This adder can be run-time configured to different reconfigurable word lengths based on the partition signal commands provided. Moreover, the design is partitioned into sub-blocks based on functionality to save power, i.e., configuring the computation only for the necessary data path, thus avoiding the unnecessary switching power from the data path computed values that do not get used. Only functions that are needed are powered on, and the rest of the functionality is powered off. The proposed 64-bit dynamically reconfigurable media signal processing (MSP) adder is implemented in the 180 nm CMOS technology at 1.8 V, requiring an area of 39,478 μm2 and a power of 79.24 mW. The dynamic MSP adder achieves a 15.7% reduction in area and a 59.2% reduction in power than the 64-bit MSP adder.

Dynamically Reconfigurable Encryption System of the AES

Reconfigurable computing has grown to become an important and large field of research, it offers advantages over traditional hardware and software implementations of computational algorithms. The Advanced Encryption Standard （AES） algorithm is widely applied in government department and commerce. This paper analyzed the AES algorithms with different cipher keys, adopted a novel key scheduler that generated the round key real-time, proposed a dynamically reconfigurable encryption system which supported the AES algorithm with different cipher keys, and designed the architecture of the reconfigurable system. The dynamically reconfigurable AES system had been realized on FPGA. The result proves that the reconfigurable AES system is flexible, lower cost and high security level.

Mission reliability modeling and evaluation for reconfigurable unmanned weapon system-of-systems based on effective operation loop

The concept of unmanned weapon system-of-systems(UWSoS)involves a collection of various unmanned systems to achieve or accomplish a specific goal or mission.The mission reliability of UWSoS is represented by its ability to finish a required mission above the baselines of a given mission.However,issues with heterogeneity,cooperation between systems,and the emergence of UWSoS cannot be effectively solved by traditional system reliability methods.This study proposes an effective operation-loop-based mission reliability evaluation method for UWSoS by analyzing dynamic reconfiguration.First,we present a new connotation of an effective operation loop by considering the allocation of operational entities and physical resource constraints.Then,we propose an effective operationloop-based mission reliability model for a heterogeneous UWSoS according to the mission baseline.Moreover,a mission reliability evaluation algorithm is proposed under random external shocks and topology reconfiguration,revealing the evolution law of the effective operation loop and mission reliability.Finally,a typical 60-unmanned-aerial-vehicle-swarm is taken as an example to demonstrate the proposed models and methods.The mission reliability is achieved by considering external shocks,which can serve as a reference for evaluating and improving the effectiveness of UWSoS.

Specification and Verification of Dynamically Reconfigurable Systems Using Dynamic Linear Hybrid Automata

A dynamically reconfigurable system can change its configuration during operation, and studies of such systems are being carried out in many fields. In particular, medical technology and aerospace engineering must ensure system safety because any defect will have serious consequences. Model checking is a method for verifying system safety. In this paper, we propose the Dynamic Linear Hybrid Automaton (DLHA) specification language and show a method to analyze reachability for a system consisting of several DLHAs.

Energy-Efficient Dynamic Configurable Datapath Architecture for IoT Devices

This paper introduces a novel RISC-V processor architecture designed for ultra-low-power and energy-efficient applications,particularly for Internet of things(IoT)devices.The architecture enables runtime dynamic reconfiguration of the datapath,allowing efficient balancing between computational performance and power consumption.This is achieved through interchangeable components and clock gating mechanisms,which help the processor adapt to varying workloads.A prototype of the architecture was implemented on a Xilinx Artix 7 field programmable gate array(FPGA).Experimental results show significant improvements in power efficiency and performance.The mini configuration achieves an impressive reduction in power consumption,using only 36%of the baseline power.Meanwhile,the full configuration boosts performance by 8%over the baseline.The flexible and adaptable nature of this architecture makes it highly suitable for a wide range of low-power IoT applications,providing an effective solution to meet the growing demands for energy efficiency in modern IoT devices.

Switchable Capacitor Bank Coordination and Dynamic Network Reconfiguration for Improving Operation of Distribution Network Integrated with Renewable Energy Resources

Point of common coupling(PCC)arrays are the most prominent and widely-used intermittent distributed generations(DGs).Due to the right-of-way,environmental,economical and other restrictions,the connection of these types of DGs to the preferred point of the distribution network is very difficult or impossible in some cases.Therefore,because of non-optimal locations,they may cause a voltage rise at the PCC.In this paper,a coordinated design of switchable capacitor banks(SCBs)with dynamic reconfiguration of the distribution network is proposed to avoid low-and high-voltage violations.The distribution network reconfiguration is implemented to mitigate the voltage rise at PCCs and capacitor banks(CBs)to solve the low-voltage problem.A novel method is presented for determining the optimal size of CBs.The proposed capacitor sizing method(CSM)effectively determines the optimal values of reactive power for the given nodes.The optimal locations of SCB are determined using particle swarm optimization algorithm.The 24-hour reactive power curve optimized by the proposed method plays a pivotal role in designing SCBs.The simulation results show that the implementation of the dynamic network reconfiguration and the placement of SCB is required to maintain a standard voltage profile for better employment of DG embedded distribution networks.

Dynamic survivable mapping through reconfiguration in IP over WDM network

A new approach for network survivability problem in Intemet protocol （IP） over wavelength division multiplexing （WDM） optical network is proposed to enhance the IP layer restorability under physical link failure through logical topology reconfiguration. More specifically, after traffic arrival and departure, reconfiguring the logical topology correspondingly is helpful to minimize the traffic disruption after physical link failure. So, in this paper, this problem is proposed for first time and formulated as an integer linear programming （ILP） problem. And then, two heuristic algorithms are proposed. The performance of proposed algorithms have been evaluated through simulations, and the results show that reconfiguring the logical topology dynamically could achieve more than 20% improvement of the restorability of traffic in IP layer, but with acceptable resource cost.

Searching for complete set of free resource rectangles on FPGA area based on CPTR

As a coprocessor, field-programmable gate array （FPGA） is the hardware computing processor accelerating the computing capacity of coraputers. To efficiently manage the hardware free resources for the placing of tasks on FPGA and take full advantage of the partially reconfigurable units, good utilization of chip resources is an important and necessary work. In this paper, a new method is proposed to find the complete set of maximal free resource rectangles based on the cross point of edge lines of running tasks on FPGA area, and the prove process is provided to make sure the correctness of this method.

Power generation maximization of distributed photovoltaic systems using dynamic topology reconfiguration

The‘mismatch losses’problem is commonly encountered in distributed photovoltaic(PV)power generation systems.It can directly reduce power generation.Hence,PV array reconfiguration techniques have become highly popular to minimize the mismatch losses.In this paper,a dynamical array reconfiguration method for Total-Cross-Ties(TCT)and Series-Parallel(SP)interconnected PV arrays is proposed.The method aims to improve the maximum power output generation of a distributed PV array in different mismatch conditions through a set of inverters and a switching matrix that is controlled by a dynamic and scalable reconfiguration optimization algorithm.The structures of the switching matrix for both TCT-based and SP-based PV arrays are designed to enable flexible alteration of the electrical connections between PV strings and inverters.Also,the proposed reconfiguration solution is scalable,because the size of the switching matrix deployed in the proposed solution is only determined by the numbers of the PV strings and the inverters,and is not related to the number of PV modules in a string.The performance of the proposed method is assessed for PV arrays with both TCT and SP interconnections in different mismatch conditions,including different partial shading and random PV module failure.The average optimization time for TCT and SP interconnected PV arrays is 0.02 and 3 s,respectively.The effectiveness of the proposed dynamical reconfiguration is confirmed,with the aver-age maximum power generation improved by 8.56%for the TCT-based PV array and 6.43%for the SP-based PV array compared to a fixed topology scheme.

Reconfigurable design of deblocking filter for variable block sizes

Based on the flexible quadtree partition structure of coding tree units(CTUs),the deblocking filter(DBF)in high efficiency video coding(HEVC)consumes a lot of resources when implemen-ted by hardware.It is difficult to achieve flexible switching between different sizes of coding blocks.Aiming at this problem,a reconfigurable implementation of DBF is proposed.Based on the dynamic programmable reconfigurable video array processor(DPRAP)with context switch reconfiguration mechanism,the runtime flexible switching of two coding block sizes is realized.The experimental results show that the highest work-frequency reaches 151.4 MHz.Compared with the dedicated hardware architecture scheme,the resource consumption can be reduced by 28.1%while realizing the dynamic switching between algorithms of two coding block sizes.Compared with the results of HM16.0,by using a complete I-frame for testing,the average peak signal-to-noise ratio(PSNR)of the reconfigurable implementation proposed in this paper has increased by 3.0508 dB,the coding quality has improved to a certain extent.

AVAILABILITY MODEL FOR SELF TEST AND REPAIR IN FAULT TOLERANT FPGA-BASED SYSTEMS

Dynamically reconfigurable Field Programmable Gate Array(dr-FPGA) based electronic systems on board mission-critical systems are highly susceptible to radiation induced hazards that may lead to faults in the logic or in the configuration memory. The aim of our research is to characterize self-test and repair processes in Fault Tolerant(FT) dr-FPGA systems in the presence of environmental faults and explore their interrelationships. We develop a Continuous Time Markov Chain(CTMC) model that captures the high level fail-repair processes on a dr-FPGA with periodic online Built-In Self-Test(BIST) and scrubbing to detect and repair faults with minimum latency. Simulation results reveal that given an average fault interval of 36 s, an optimum self-test interval of 48.3 s drives the system to spend 13% of its time in self-tests, remain in safe working states for 76% of its time and face risky fault-prone states for only 7% of its time. Further, we demonstrate that a well-tuned repair strategy boosts overall system availability, minimizes the occurrence of unsafe states, and accommodates a larger range of fault rates within which the system availability remains stable within 10% of its maximum level.