Field Programmable Gate Array(FPGA) and Single Instruction Multiple Data(SIMD) processing array share many architecture features. In both architectures, an array is employed to provide high speed computation. In this ...Field Programmable Gate Array(FPGA) and Single Instruction Multiple Data(SIMD) processing array share many architecture features. In both architectures, an array is employed to provide high speed computation. In this paper we show that the implementation of a Single Instruction Multiple Data (SIMD) machine the ABC 90 using the Field Programmable Gate Array (FPGA) is not completely suitable because of its characteristics. The comparison between the programmable gate arrays show that, they have many architectures features in common. Within this framework, we examine the differences and similarities between these array structures and touch upon techniques and lessons which can be done between these architectures in order to choose the appropriate Programmable gate array to implement a general purpose parallel computer. In this paper we introduce the principal of the Dynamically Programmable Date Array(DPGA) which combines the best feature of the FPGA and the SIMD arrays into a single array architecture. By the same way we show that the DPGA is more appropriate then the FPGA for wiring, hardwiring the general purpose parallel computers: SIMD and its implementation.展开更多
Reconfigurable computing has grown to become an important and large field of research, it offers advantages over traditional hardware and software implementations of computational algorithms. The Advanced Encryption S...Reconfigurable computing has grown to become an important and large field of research, it offers advantages over traditional hardware and software implementations of computational algorithms. The Advanced Encryption Standard (AES) algorithm is widely applied in government department and commerce. This paper analyzed the AES algorithms with different cipher keys, adopted a novel key scheduler that generated the round key real-time, proposed a dynamically reconfigurable encryption system which supported the AES algorithm with different cipher keys, and designed the architecture of the reconfigurable system. The dynamically reconfigurable AES system had been realized on FPGA. The result proves that the reconfigurable AES system is flexible, lower cost and high security level.展开更多
High performance computer is often required by model predictive control(MPC) systems due to the heavy online computation burden.To extend MPC to more application cases with low-cost computation facilities, the impleme...High performance computer is often required by model predictive control(MPC) systems due to the heavy online computation burden.To extend MPC to more application cases with low-cost computation facilities, the implementation of MPC controller on field programmable gate array(FPGA) system is studied.For the dynamic matrix control(DMC) algorithm,the main design idea and the implemental strategy of DMC controller are introduced based on a FPGA’s embedded system.The performance tests show that both the computation efficiency and the accuracy of the proposed controller can be satisfied due to the parallel computing capability of FPGA.展开更多
As a coprocessor,field-programmable gate array(FPGA)is the hardware computing processor accelerating the computing capacity of computers.To efficiently manage the hardware free resources for the placing of tasks on FP...As a coprocessor,field-programmable gate array(FPGA)is the hardware computing processor accelerating the computing capacity of computers.To efficiently manage the hardware free resources for the placing of tasks on FPGA and take full advantage of the partially reconfigurable units,good utilization of chip resources is an important and necessary work.In this paper,a new method is proposed to find the complete set of maximal free resource rectangles based on the cross point of edge lines of running tasks on FPGA area,and the prove process is provided to make sure the correctness of this method.展开更多
High-speed real-time digital frequency analysis is one major field of Fast Fourier Transform(FFT)application,such as Synthetic Aperture Radar(SAR)processing and medical imaging.In SAR processing,the image size could b...High-speed real-time digital frequency analysis is one major field of Fast Fourier Transform(FFT)application,such as Synthetic Aperture Radar(SAR)processing and medical imaging.In SAR processing,the image size could be 4 k×4 k in normal and it has become larger over the years.In the view of real-time,extensibility and reusable characteristics,an Field Programmable Gate Array(FPGA)based multi-channel variable-length FFT architecture which adopts radix-2 butterfly algorithm is proposed in this paper.The hardware implementation of FFT is partially reconfigurable architecture.Firstly,the proposed architecture in the paper has flexibility in terms of chip area,speed,resource utilization and power consumption.Secondly,the proposed architecture combines serial and parallel methods in its butterfly computations.Furthermore,on system-level issue,the proposed architecture takes advantage of state processing in serial mode and data processing in parallel mode.In case of sufficient FPGA resources,state processing of serial mode mentioned above is converted to pipeline mode.State processing of pipeline mode achieves high throughput.展开更多
Dynamically reconfigurable Field Programmable Gate Array(dr-FPGA) based electronic systems on board mission-critical systems are highly susceptible to radiation induced hazards that may lead to faults in the logic or ...Dynamically reconfigurable Field Programmable Gate Array(dr-FPGA) based electronic systems on board mission-critical systems are highly susceptible to radiation induced hazards that may lead to faults in the logic or in the configuration memory. The aim of our research is to characterize self-test and repair processes in Fault Tolerant(FT) dr-FPGA systems in the presence of environmental faults and explore their interrelationships. We develop a Continuous Time Markov Chain(CTMC) model that captures the high level fail-repair processes on a dr-FPGA with periodic online Built-In Self-Test(BIST) and scrubbing to detect and repair faults with minimum latency. Simulation results reveal that given an average fault interval of 36 s, an optimum self-test interval of 48.3 s drives the system to spend 13% of its time in self-tests, remain in safe working states for 76% of its time and face risky fault-prone states for only 7% of its time. Further, we demonstrate that a well-tuned repair strategy boosts overall system availability, minimizes the occurrence of unsafe states, and accommodates a larger range of fault rates within which the system availability remains stable within 10% of its maximum level.展开更多
文摘Field Programmable Gate Array(FPGA) and Single Instruction Multiple Data(SIMD) processing array share many architecture features. In both architectures, an array is employed to provide high speed computation. In this paper we show that the implementation of a Single Instruction Multiple Data (SIMD) machine the ABC 90 using the Field Programmable Gate Array (FPGA) is not completely suitable because of its characteristics. The comparison between the programmable gate arrays show that, they have many architectures features in common. Within this framework, we examine the differences and similarities between these array structures and touch upon techniques and lessons which can be done between these architectures in order to choose the appropriate Programmable gate array to implement a general purpose parallel computer. In this paper we introduce the principal of the Dynamically Programmable Date Array(DPGA) which combines the best feature of the FPGA and the SIMD arrays into a single array architecture. By the same way we show that the DPGA is more appropriate then the FPGA for wiring, hardwiring the general purpose parallel computers: SIMD and its implementation.
基金Supported by the National Natural Science Foun-dation of China (60374008)
文摘Reconfigurable computing has grown to become an important and large field of research, it offers advantages over traditional hardware and software implementations of computational algorithms. The Advanced Encryption Standard (AES) algorithm is widely applied in government department and commerce. This paper analyzed the AES algorithms with different cipher keys, adopted a novel key scheduler that generated the round key real-time, proposed a dynamically reconfigurable encryption system which supported the AES algorithm with different cipher keys, and designed the architecture of the reconfigurable system. The dynamically reconfigurable AES system had been realized on FPGA. The result proves that the reconfigurable AES system is flexible, lower cost and high security level.
基金the National Science Foundation of China(Nos.60934007 and 61074060)the Postdoctoral Science Foundation of China(No.20090460627)+2 种基金the Postdoctoral Scientific Program of Shanghai (No.10R21414600)the Specialized Research Fund for the Doctoral Program of Higher Education (No.20070248004)the China Postdoctoral Science Foundation Special Support(No.201003272)
文摘High performance computer is often required by model predictive control(MPC) systems due to the heavy online computation burden.To extend MPC to more application cases with low-cost computation facilities, the implementation of MPC controller on field programmable gate array(FPGA) system is studied.For the dynamic matrix control(DMC) algorithm,the main design idea and the implemental strategy of DMC controller are introduced based on a FPGA’s embedded system.The performance tests show that both the computation efficiency and the accuracy of the proposed controller can be satisfied due to the parallel computing capability of FPGA.
基金Project supported by the Shanghai Leading Academic Discipline Project(Grant No.J50103)the Natural Science Foundation of Jiangxi Province(Grant No.2010GZS0031)the Science Technology Project of Jiangxi Province(Grant No.2010BGB00604)
文摘As a coprocessor,field-programmable gate array(FPGA)is the hardware computing processor accelerating the computing capacity of computers.To efficiently manage the hardware free resources for the placing of tasks on FPGA and take full advantage of the partially reconfigurable units,good utilization of chip resources is an important and necessary work.In this paper,a new method is proposed to find the complete set of maximal free resource rectangles based on the cross point of edge lines of running tasks on FPGA area,and the prove process is provided to make sure the correctness of this method.
基金The work was supported by National Natural Science Foundation of China(61271149)and by Beijing Natural Science Foundation(4144093)
文摘High-speed real-time digital frequency analysis is one major field of Fast Fourier Transform(FFT)application,such as Synthetic Aperture Radar(SAR)processing and medical imaging.In SAR processing,the image size could be 4 k×4 k in normal and it has become larger over the years.In the view of real-time,extensibility and reusable characteristics,an Field Programmable Gate Array(FPGA)based multi-channel variable-length FFT architecture which adopts radix-2 butterfly algorithm is proposed in this paper.The hardware implementation of FFT is partially reconfigurable architecture.Firstly,the proposed architecture in the paper has flexibility in terms of chip area,speed,resource utilization and power consumption.Secondly,the proposed architecture combines serial and parallel methods in its butterfly computations.Furthermore,on system-level issue,the proposed architecture takes advantage of state processing in serial mode and data processing in parallel mode.In case of sufficient FPGA resources,state processing of serial mode mentioned above is converted to pipeline mode.State processing of pipeline mode achieves high throughput.
文摘Dynamically reconfigurable Field Programmable Gate Array(dr-FPGA) based electronic systems on board mission-critical systems are highly susceptible to radiation induced hazards that may lead to faults in the logic or in the configuration memory. The aim of our research is to characterize self-test and repair processes in Fault Tolerant(FT) dr-FPGA systems in the presence of environmental faults and explore their interrelationships. We develop a Continuous Time Markov Chain(CTMC) model that captures the high level fail-repair processes on a dr-FPGA with periodic online Built-In Self-Test(BIST) and scrubbing to detect and repair faults with minimum latency. Simulation results reveal that given an average fault interval of 36 s, an optimum self-test interval of 48.3 s drives the system to spend 13% of its time in self-tests, remain in safe working states for 76% of its time and face risky fault-prone states for only 7% of its time. Further, we demonstrate that a well-tuned repair strategy boosts overall system availability, minimizes the occurrence of unsafe states, and accommodates a larger range of fault rates within which the system availability remains stable within 10% of its maximum level.
