Class E变换器结构简单,变换效率高,有良好的发展前景。论文将磁集成技术应用到隔离型Class E变换器中,减小磁性元件的体积、重量、提高变换器的功率密度。文中详细分析了利用变压器漏感以及采用独立绕组两种磁集成方案,在此基础上,制...Class E变换器结构简单,变换效率高,有良好的发展前景。论文将磁集成技术应用到隔离型Class E变换器中,减小磁性元件的体积、重量、提高变换器的功率密度。文中详细分析了利用变压器漏感以及采用独立绕组两种磁集成方案,在此基础上,制作了输入12V、输出功率21W、输出电流0.43A的原理样机,通过实验验证了磁集成方案的有效性,从实验结果可以得出采用磁集成技术后,变换器中磁件的体积和重量明显降低,且变换器的效率有所提高。展开更多
Studies In model plants showed that SEPALLATA （SEP） genes are required for the Identification of floral organs and the determination of floral meristems In Arabidopsis. In this paper a SEP homolog, TrSEP3, was Isola...Studies In model plants showed that SEPALLATA （SEP） genes are required for the Identification of floral organs and the determination of floral meristems In Arabidopsis. In this paper a SEP homolog, TrSEP3, was Isolated from a China-specific species, Taihangla rupestrisi Yü et LI. Phylogenetlc analysis showed that the gene belongs to the SEP3-clade of SEP （previous AGL2） subfamily. In situ hybridization was used to reveal the potential functional specification, and the results showed that TrSEP3 expression was first observed in floral meristems and then confined to the floral primordla of the three inner whorls. In the matured flower, TrSEP3 was strongly expressed In the tips of pistils and weak In stamens and petals. The evolution force analysis shows that TrSEP3 might undergo a relaxed negative selection. These results suggested that TrSEP3 may not only function In determining the identity of floral merlstems and the primordia of three inner whorls, but also function In matured reproductive organs.展开更多
We present and propose a complete and iterative integrated-circuit and electro-magnetic（EM） co-design methodology and procedure for a low-voltage sub-1 GHz class-E PA.The presented class-E PA consists of the onchip ...We present and propose a complete and iterative integrated-circuit and electro-magnetic（EM） co-design methodology and procedure for a low-voltage sub-1 GHz class-E PA.The presented class-E PA consists of the onchip power transistor,the on-chip gate driving circuits,the off-chip tunable LC load network and the off-chip LC ladder low pass filter.The design methodology includes an explicit design equation based circuit components values＇ analysis and numerical derivation,output power targeted transistor size and low pass filter design,and power efficiency oriented design optimization.The proposed design procedure includes the power efficiency oriented LC network tuning,the detailed circuit/EM co-simulation plan on integrated circuit level,package level and PCB level to ensure an accurate simulation to measurement match and first pass design success.The proposed PA is targeted to achieve more than 15 dBm output power delivery and 40% power efficiency at 433 MHz frequency band with 1.5 V low voltage supply.The LC load network is designed to be off-chip for the purpose of easy tuning and optimization.The same circuit can be extended to all sub-1 GHz applications with the same tuning and optimization on the load network at different frequencies.The amplifier is implemented in 0.13 μm CMOS technology with a core area occupation of 400 μm by 300 μm.Measurement results showed that it provided power delivery of 16.42 dBm at antenna with efficiency of 40.6%.A harmonics suppression of 44 dBc is achieved,making it suitable for massive deployment of IoT devices.展开更多
This paper presents a 1.8 GHz class-E controlled power amplifier (PA). The proposed power amplifier is designed with two-stage architecture. The main advantage of the proposed technique for output control power is a h...This paper presents a 1.8 GHz class-E controlled power amplifier (PA). The proposed power amplifier is designed with two-stage architecture. The main advantage of the proposed technique for output control power is a high 37 dB output power dynamic range with good average power adding efficiency. The measurement results show that the PA achieves a high power gain of 23 dBm and power added efficiency (PAE) by 38%. The circuit was post layout simulated in a standard 0.18 μm CMOS technology.展开更多
基金Supported by the State Key Basic Research and Development Plan of China （2006CB100202） and the National Natural Science Foundation of China （30170093）.Acknowledgements The authors would like to thank Dr Gui-Sheng Li （Institute of Genetics and Developmental Biology, the Chinese Academy of Sciences） for his helping on the analysis of selection force Dr Shihua Shen （Institute of Botany, the Chinese Academy of Sciences） for providing background information of Taihangia, and Dr Chun-Ming Liu for critical reading.
文摘Studies In model plants showed that SEPALLATA （SEP） genes are required for the Identification of floral organs and the determination of floral meristems In Arabidopsis. In this paper a SEP homolog, TrSEP3, was Isolated from a China-specific species, Taihangla rupestrisi Yü et LI. Phylogenetlc analysis showed that the gene belongs to the SEP3-clade of SEP （previous AGL2） subfamily. In situ hybridization was used to reveal the potential functional specification, and the results showed that TrSEP3 expression was first observed in floral meristems and then confined to the floral primordla of the three inner whorls. In the matured flower, TrSEP3 was strongly expressed In the tips of pistils and weak In stamens and petals. The evolution force analysis shows that TrSEP3 might undergo a relaxed negative selection. These results suggested that TrSEP3 may not only function In determining the identity of floral merlstems and the primordia of three inner whorls, but also function In matured reproductive organs.
基金supported by the National Natural Science Foundation of China(No.61574125)the Industry Innovation Project of Suzhou City of China(No.SYG201641)
文摘We present and propose a complete and iterative integrated-circuit and electro-magnetic（EM） co-design methodology and procedure for a low-voltage sub-1 GHz class-E PA.The presented class-E PA consists of the onchip power transistor,the on-chip gate driving circuits,the off-chip tunable LC load network and the off-chip LC ladder low pass filter.The design methodology includes an explicit design equation based circuit components values＇ analysis and numerical derivation,output power targeted transistor size and low pass filter design,and power efficiency oriented design optimization.The proposed design procedure includes the power efficiency oriented LC network tuning,the detailed circuit/EM co-simulation plan on integrated circuit level,package level and PCB level to ensure an accurate simulation to measurement match and first pass design success.The proposed PA is targeted to achieve more than 15 dBm output power delivery and 40% power efficiency at 433 MHz frequency band with 1.5 V low voltage supply.The LC load network is designed to be off-chip for the purpose of easy tuning and optimization.The same circuit can be extended to all sub-1 GHz applications with the same tuning and optimization on the load network at different frequencies.The amplifier is implemented in 0.13 μm CMOS technology with a core area occupation of 400 μm by 300 μm.Measurement results showed that it provided power delivery of 16.42 dBm at antenna with efficiency of 40.6%.A harmonics suppression of 44 dBc is achieved,making it suitable for massive deployment of IoT devices.
文摘This paper presents a 1.8 GHz class-E controlled power amplifier (PA). The proposed power amplifier is designed with two-stage architecture. The main advantage of the proposed technique for output control power is a high 37 dB output power dynamic range with good average power adding efficiency. The measurement results show that the PA achieves a high power gain of 23 dBm and power added efficiency (PAE) by 38%. The circuit was post layout simulated in a standard 0.18 μm CMOS technology.
