On a Parasitic Bipolar Transistor Action in a Diode ESD Protection Device

In this work, we show that an excessive lattice heating problem can occur in the diode electrostatic discharge (ESD) protection device connected to a VDD bus in the popular diode input protection scheme, which is favorably used in CMOS RF ICs. To figure out the reason for the excessive lattice heating, we construct an equivalent circuit for input human-body model (HBM) test environment of a CMOS chip equipped with the diode protection circuit, and execute mixed-mode transient simulations utilizing a 2-D device simulator. We analyze the simulation results in detail to show out that a parasitic pnp bipolar transistor action relating nearby p+-substrate contacts is responsible for the excessive lattice heating in the diode protection device, which has never been focused before anywhere.

Design and optimization of CMOS LNA with ESD protection for 2.4 GHz WSN application

A new optimization method of a source inductive degenerated low noise amplifier（LNA） with electrostatic discharge protection is proposed.It can achieve power-constrained simultaneous noise and input matching. An analysis of the input impedance and the noise parameters is also given.Based on the developed method,a 2.4 GHz LNA for wireless sensor network application is designed and optimized using 0.18-μm RF CMOS technology. The measured results show that the LNA achieves a noise figure of 1.59 dB,a power gain of 14.12 dB, an input 1 dB compression point of-8 dBm and an input third-order intercept point of 1 dBm.The DC current is 4 mA under a supply of 1.8 V.

Whole-Chip ESD Protection Design for RF and AMS ICs

As integrated circuits （IC） technologies advance into very-deep-sub-micron （VDSM）, electrostatic discharge （ESD） failure becomes one of the most devastating IC reliability problems and on-chip ESD protection design emerges as a major challenge to radio frequency （RF）, analog, and mixed-signal （AMS） IC designs. This paper reviews key design aspects and recent advances in whole-chip ESD protection designs for RF/AMS IC applications in CMOS technologies.

Design and investigation of novel ultra-high-voltage junction field-effect transistor embedded with NPN

Ultra-high-voltage(UHV)junction field-effect transistors(JFETs)embedded separately with the lateral NPN(JFETLNPN),and the lateral and vertical NPN(JFET-LVNPN),are demonstrated experimentally for improving the electrostatic discharge(ESD)robustness.The ESD characteristics show that both JFET-LNPN and JFET-LVNPN can pass the 5.5-k V human body model(HBM)test.The JFETs embedded with different NPNs have 3.75 times stronger in ESD robustness than the conventional JFET.The failure analysis of the devices is performed with scanning electron microscopy,and the obtained delayer images illustrate that the JFETs embedded with NPN transistors have good voltage endurance capabilities.Finally,the internal physical mechanism of the JFETs embedded with different NPNs is investigated with emission microscopy and Sentaurus simulation,and the results confirm that the JFET-LVNPN has stronger ESD robustness than the JFET-LNPN,because the vertical NPN has a better electron collecting capacity.The JFET-LVNPN is helpful in providing a strong ESD protection and functions for a power device.

A novel latch-up free SCR-LDMOS with high holding voltage for a power-rail ESD clamp

The low snapback holding voltage of the SCR-LDMOS device makes it susceptible to latch-up failure,when used in power-rail ESD（electro-static discharge） clamp circuits.In order to eliminate latch-up risk,this work presents a novel SCR-LDMOS structure with an N-type implantation layer to achieve a 17 V holding voltage and a 5.2 A second breakdown current.The device has been validated using TLP measurement analysis and is applied to a power-rail ESD clamp in half-bridge driver ICs.

ESD-Induced Noise to Low Noise Amplifier Circuits in BiCMOS

Electrostatic discharge （ESD） induced parasitic effects have serious impacts on performance of radio frequency （RF） integrated circuits （IC）. This paper discusses a comprehensive noise analysis procedure for ESD protection structures and their negative influences on RF ICs. Noise figures （NFs） of commonly used ESD protection structures and their impacts on a single-chip 5.5 GHz low-noise amplifier （LNA） circuit were depicted. A design example in 0.18 μm SiGe BiCMOS was presented. Measurement results confirm that significant noise degradation occurs in the LNA circuit due to ESD-induced noise effects. A practical design procedure for ESD-protected RF ICs is provided for real-world RF IC optimization.

Study of the effect of switching speed of the a-SiC/c-Si(p)-based,thyristor-like,ultrahigh-speed switches,using two-dimensional simulation techniques

A parametric study for a series of technological and geometrical parameters affecting rise time of Al/aSiC/c-Si（p）/c-Si（n~＋）/Al thyristor-like switches,is presented here for the first time,using two-dimensional simulation techniques.By varying anode current values in simulation procedure we achieved very good agreement between simulation and experimental results for the rising time characteristics of the switch.A series of factors affecting the rising time of the switches are studied here.Two factors among all others studied here,exerting most significant influence,of more than one order of magnitude on the rising time,are a-SiC and c-Si（p） region widths,validating our earlier presented model for device operation.The above widths can be easily varied on device manufacture procedure.We also successfully simulated the rising time characteristics of our earlier presented simulated improved switch,with forward breakover voltage V（BF） = 11 V and forward voltage drop VF = 9.5 V at the ON state,exhibiting an ultra low rise time value of less than 10 ps,which in conjunction with its high anode current density values of 12 A/mm^2 and also cheap and easy fabrication techniques,makes this switch appropriate for ESD protection as well as RF MEMS and NEMS applications.

An IO block array in a radiation-hardened SOI SRAM-based FPGA

We present an input/output block （lOB） array used in the radiation-hardened SRAM-based field- programmable gate array （FPGA） VS1000, which is designed and fabricated with a 0.5 μm partially depleted silicon-on-insulator （SOI） logic process at the CETC 58th Institute. Corresponding with the characteristics of the FPGA, each IOB includes a local routing pool and two IO cells composed of a signal path circuit, configurable input/output buffers and an ESD protection network. A boundary-scan path circuit can be used between the pro- grammable buffers and the input/output circuit or as a transparent circuit when the IOB is applied in different modes. Programmable IO buffers can be used at TTL/CMOS standard levels. The local routing pool enhances the flexibility and routability of the connection between the IOB array and the core logic. Radiation-hardened designs, including A-type and H-type body-tied transistors and special D-type registers, improve the anti-radiation performance. The ESD protection network, which provides a high-impulse discharge path on a pad, prevents the breakdown of the core logic caused by the immense current. These design strategies facilitate the design of FPGAs with different ca- pacities or architectures to form a series of FPGAs. The functionality and performance of the IOB array is proved after a functional test. The radiation test indicates that the proposed VS 1000 chip with an IOB array has a total dose tolerance of 100 krad（Si）, a dose survivability rate of 1.5 × 10^11 rad（Si）/s, and a neutron fluence immunity of 1×10^14 n/cm2.