提高集成电路ESD防护能力的仿真方法

为解决集成电路的全芯片静电防护设计中寄生电阻导致的防护空间压缩问题,提出了一种实用的能够在版图设计过程中提高集成电路静电放电(ESD)防护能力的仿真方法,用于评估和控制ESD电流通路上的寄生电阻,辅助ESD防护设计,预估器件静电防护等级。详细介绍了仿真方法的原理和流程,以0.18μm SOI CMOS工艺制造的静态随机存储器电路为仿真和实验对象,应用此仿真方法,统计寄生电阻值,优化ESD防护设计,并进行ESD测试,记录未优化样品和优化样品的失效电压。通过对比寄生电阻和失效电压,证明降低寄生电阻可获得更好的ESD防护性能,而且器件失效电压和关键寄生电阻值R Vdd之间存在近似线性反比关系。

CMOS电路中ESD保护结构的设计

本文研究了在CMOS工艺中I/O电路的ESD保护结构设计以及相关版图的要求,其中重点讨论了PAD到VSS电流通路的建立。

Design and analysis of a NMOS triggered LIGBT structure for electrostatic discharge protection

A novel NMOS triggered LIGBT(NTLIGBT) structure is proposed for electrostatic discharge(ESD) protection in this paper. The structure utilizes internal NMOS to trigger SCR-like structure in LIGBT. The trigger voltage is significantly reduced because the embedded NMOS causes N+-drain/P-body junction being apt to avalanche breakdown. At the same time, the new parasitic PNP transistor including the newly added P+-region as a collector forms another path to bleed ESD current and then the conductivity modulation in the LIGBT is weakened. As a result, the holding voltage is increased. So, the proposed NTLIGBT structure has a narrow ESD design window. The simulation results show an improvement of 71.5% in trigger voltage and over 50% in holding voltage comparing with the conventional LIGBT structure.

A novel double-trench LVTSCR used in the ESD protection of a RFIC

A low-voltage triggering silicon-controlled rectifier（LVTSCR）,for its high efficiency and low parasitic parameters,has many advantages in ESD protection,especially in ultra-deep sub-micron（UDSM） IC and high frequency applications.In this paper,the impact factors of the snapback characteristics of a LVTSCR and the configuring modes are analyzed and evaluated in detail.These parameters include anode series resistance,gate voltage,structure and size of devices.In addition,a double-trench LVTSCR is presented that can increase the hold-on voltage effectively and offers easy adjustment.Also,its snapback characteristics can obey the ESD design window rule very well.The strategy of ESD protection in a RFIC using a LVTSCR is discussed at the end of the paper.

A novel HBT trigger SCR in 0.35 μm SiGe BiCMOS technology

The silicon-controlled rectifier（SCR） device is known as an efficient electrostatic discharge（ESD） protection device due to the highest ESD robustness in the smallest layout area. However, SCR has some drawbacks,such as high trigger voltage and low holding voltage. In order to reduce the trigger voltage of the SCR device for ESD protection, a new heterojunction bipolar transistor（HBT） trigger silicon controlled rectifier（HTSCR） device in 0.35 m Si Ge Bi CMOS technology are proposed. The underlying physical mechanisms critical to the trigger voltage are demonstrated based on transmission line pulsing（TLP） measurement and physics-based simulation results. The simulation results prove that the trigger voltage of the HTSCR is decided by the collector-to-emitter breakdown voltage of the HBT structure in floating base configuration. The ESD experiment test results demonstrate the HTSCR can offer superior performance with a small trigger voltage, an adjustable holding voltage and a high ESD robustness. In comparison to the conventional MLSCR, the trigger voltage of the fabricated HTSCR can reduce to less than 50% of that of the MLSCR, and the I_（t2） of the HBT trigger SCR is 80% more than that of the MLSCR.