Novel LDNMOS embedded SCR with strong ESD robustness based on 0.5 μm 18 V CDMOS technology

A novel LDNMOS embedded silicon controlled rectifier(SCR) was proposed to enhance ESD robustness of high-voltage(HV) LDNMOS based on a 0.5 μm 18 V CDMOS process. A two-dimensional(2D) device simulation and a transmission line pulse(TLP) testing were used to analyze the working mechanism and ESD performance of the novel device. Compared with the traditional GG-LDNMOS, the secondary breakdown current(It2) of the proposed device can successfully increase from 1.146 A to 3.169 A with a total width of 50 μm, and ESD current discharge efficiency is improved from 0.459 m A/μm2 to 1.884 m A/μm2. Moreover, due to their different turn-on resistances(Ron), the device with smaller channel length(L) owns a stronger ESD robustness per unit area.

Design and investigation of novel ultra-high-voltage junction field-effect transistor embedded with NPN

Ultra-high-voltage(UHV)junction field-effect transistors(JFETs)embedded separately with the lateral NPN(JFETLNPN),and the lateral and vertical NPN(JFET-LVNPN),are demonstrated experimentally for improving the electrostatic discharge(ESD)robustness.The ESD characteristics show that both JFET-LNPN and JFET-LVNPN can pass the 5.5-k V human body model(HBM)test.The JFETs embedded with different NPNs have 3.75 times stronger in ESD robustness than the conventional JFET.The failure analysis of the devices is performed with scanning electron microscopy,and the obtained delayer images illustrate that the JFETs embedded with NPN transistors have good voltage endurance capabilities.Finally,the internal physical mechanism of the JFETs embedded with different NPNs is investigated with emission microscopy and Sentaurus simulation,and the results confirm that the JFET-LVNPN has stronger ESD robustness than the JFET-LNPN,because the vertical NPN has a better electron collecting capacity.The JFET-LVNPN is helpful in providing a strong ESD protection and functions for a power device.

A novel latch-up free SCR-LDMOS with high holding voltage for a power-rail ESD clamp

The low snapback holding voltage of the SCR-LDMOS device makes it susceptible to latch-up failure,when used in power-rail ESD（electro-static discharge） clamp circuits.In order to eliminate latch-up risk,this work presents a novel SCR-LDMOS structure with an N-type implantation layer to achieve a 17 V holding voltage and a 5.2 A second breakdown current.The device has been validated using TLP measurement analysis and is applied to a power-rail ESD clamp in half-bridge driver ICs.

Research and optimization of the ESD response characteristic in a ps-LDMOS transistor

The ESD response characteristic in a p-type symmetric lateral DMOS （ps-LDMOS） has been investigated. The experimental results show that the ps-LDMOS has weak ESD robustness due to an absence of the ＂snapback＂ characteristic. In addition, the location of the hot spot changes little for the special device. The method for reducing the lattice temperature of the hot spot can be used to enhance the ESD capacity of the ps-LDMOS, thereby, a novel and easily-achievable ps-LDMOS structure with a p-type lightly doped drain （p-LDD） has been proposed. The special region p-LDD lowers the electric field at the edge of the poly gate, making the whole dis- tribution of the surface electric field more uniform. Therefore, the ESD robustness is improved two times and no obvious change of other electric parameters is introduced.