Effect and mechanism of on-chip electrostatic discharge protection circuit under fast rising time electromagnetic pulse

The electrostatic discharge(ESD)protection circuit widely exists in the input and output ports of CMOS digital circuits,and fast rising time electromagnetic pulse(FREMP)coupled into the device not only interacts with the CMOS circuit,but also acts on the protection circuit.This paper establishes a model of on-chip CMOS electrostatic discharge protection circuit and selects square pulse as the FREMP signals.Based on multiple physical parameter models,it depicts the distribution of the lattice temperature,current density,and electric field intensity inside the device.At the same time,this paper explores the changes of the internal devices in the circuit under the injection of fast rising time electromagnetic pulse and describes the relationship between the damage amplitude threshold and the pulse width.The results show that the ESD protection circuit has potential damage risk,and the injection of FREMP leads to irreversible heat loss inside the circuit.In addition,pulse signals with different attributes will change the damage threshold of the circuit.These results provide an important reference for further evaluation of the influence of electromagnetic environment on the chip,which is helpful to carry out the reliability enhancement research of ESD protection circuit.

Assessment of electrostatic discharge sensitivity of nitrogen-rich heterocyclic energetic compounds and their salts as high energy-density dangerous compounds:A study of structural variables

Nitrogen-rich heterocyclic energetic compounds(NRHECs)and their salts have witnessed widespread synthesis in recent years.The substantial energy-density content within these compounds can lead to potentially dangerous explosive reactions when subjected to external stimuli such as electrical discharge.Therefore,developing a reliable model for predicting their electrostatic discharge sensitivity(ESD)becomes imperative.This study proposes a novel and straightforward model based on the presence of specific groups(-NH_(2) or-NH-,-N=N^(+)-O^(-)and-NNO_(2),-ONO_(2) or-NO_(2))under certain conditions to assess the ESD of NRHECs and their salts,employing interpretable structural parameters.Utilizing a comprehensive dataset comprising 54 ESD measurements of NRHECs and their salts,divided into 49/5 training/test sets,the model achieves promising results.The Root Mean Square Error(RMSE),Mean Absolute Error(MAE),and Maximum Error for the training set are reported as 0.16 J,0.12 J,and 0.5 J,respectively.Notably,the ratios RMSE(training)/RMSE(test),MAE(training)/MAE(test),and Max Error(training)/Max Error(test)are all greater than 1.0,indicating the robust predictive capabilities of the model.The presented model demonstrates its efficacy in providing a reliable assessment of ESD for the targeted NRHECs and their salts,without the need for intricate computer codes or expert involvement.

Dynamic electrostatic-discharge path investigation relied on different impact energies in metal-oxide-semiconductor circuits

Gate-grounded n-channel metal-oxide-semiconductor(GGNMOS)devices have been widely implemented as power clamps to protect semiconductor devices from electrostatic discharge stress owing to their simple construction,easy triggering,and low power dissipation.We present a novel I-V characterization of the GGNMOS used as the power clamp in complementary metal-oxide-semiconductor circuits as a result of switching the ESD paths under different impact energies.This special effect could cause an unexpected latch-up or pre-failure phenomenon in some applications with relatively large capacitances from power supply to power ground,and thus should be urgently analyzed and resolved.Transmission-linepulse,human-body-modal,and light-emission tests were performed to explore the root cause.

Enhancement of holding voltage by a modified low-voltage trigger silicon-controlled rectifier structure for electrostatic discharge protection

A novel structure of low-voltage trigger silicon-controlled rectifiers(LVTSCRs) with low trigger voltage and high holding voltage is proposed for electrostatic discharge(ESD) protection. The proposed ESD protection device possesses an ESD implant and a floating structure. This improvement enhances the current discharge capability of the gate-grounded NMOS and weakens the current gain of the silicon-controlled rectifier current path. According to the simulation results, the proposed device retains a low trigger voltage characteristic of LVTSCRs and simultaneously increases the holding voltage to 5.53 V, providing an effective way to meet the ESD protection requirement of the 5 V CMOS process.

高压GGNMOS器件结构及工艺对ESD防护特性的影响

基于高压CMOS工艺,对高压栅极接地N型金属氧化物半导体(Highvoltagegrounded-gate N-metal-oxide-semiconductor, HV-GGNMOS)的静电放电(Electrostatic discharge, ESD)防护性能进行研究。由于强折回特性以及失效电流低,HV-GGNMOS在实际应用中受到限制。本文通过计算机辅助设计技术仿真及传输线脉冲实验研究了工艺参数及版图结构对器件ESD防护性能的影响。结果表明,增加漂移区掺杂浓度可以有效提高器件失效电流;加强体接触和增加漂移区长度可以提高器件的维持电压,但失效电流会有所下降,占用版图面积也会更大。

一种具有高ESD泄放电流的AlGaN/GaN HEMT器件

为满足AlGaN/GaN HEMT器件的高静电放电(Electrostatic discharge, ESD)防护需求,提出了一种用于泄放静电电荷的具有掺杂沟槽的GaN HEMT防护结构。通过在沟道层下方引入沟槽,提高了GaN HEMT在面对ESD事件时的电流泄放能力,同时将沟槽设置在栅极与漏极之间,降低了沟槽对栅极控制的影响,保证了栅极的稳定性。对所提结构在ESD条件下的电流泄放能力进行了仿真验证,结果表明,相比于常规的GaN HEMT结构,沟槽结构GaN HEMT的泄放电流提高了32.7%,并且当沟槽与栅极距离大于0.3μm时,沟槽对阈值电压几乎没有影响。

Enhanced gated-diode-triggered silicon-controlled rectifier for robust electrostatic discharge (ESD) protection applications

A robust electron device called the enhanced gated-diode-triggered silicon-controlled rectifier (EGDTSCR) for electrostatic discharge (ESD) protection applications has been proposed and implemented in a 0.18-μm 5-V/24-V BCD process. The proposed EGDTSCR is constructed by adding two gated diodes into a conventional ESD device called the modified lateral silicon-controlled rectifier (MLSCR). With the shunting effect of the surface gated diode path, the proposed EGDTSCR, with a width of 50 μm, exhibits a higher failure current (i.e., 3.82 A) as well as a higher holding voltage (i.e., 10.21 V) than the MLSCR.

Study on electrostatic discharge(ESD)characteristics of ultra-thin dielectric film

Electrostatic discharge(ESD)event usually destroys the electrical properties of dielectric films,resulting in product failure.In this work,the breakdown characteristic of machine mode(MM)ESD on three different nano size films of head gimble assemble are obtained experimentally.The breakdown voltage and thickness parameters show a positive proportional relationship,but they are generally very low and have large discrete characteristics(~30%).The maximum and minimum breakdown voltages of the tested samples are 1.08 V and 0.46 V,which are far lower than the requirement of the current standard(25 V).In addition,the judgment criterion of product damage is given,and the relationship between discharge voltage polarity,initial resistance and breakdown voltage is studied.Finally,the theoretical analysis of the breakdown characteristic law has been given.

基于工业数据挖掘的ESD软失效分析

针对电子产品出货后出现ESD软失效而导致的退货现象,文章通过机器学习算法分析产品ICT电性能测试参数、生产线ESD防护监控数据和产品ESD软失效的相关性。集成算法模型经过优化,分类准确率达到0.88,可以用于量产电子产品的ESD软失效的识别和出货风险管控。同时,利用ESD防护监控点风险指数数据集可以提高产品ESD软失效的识别准确率(8.6%)。安装部署基于物联网技术的静电放电防护监控系统,对管控电子产品生产过程中的ESD软失效风险以及控制出货风险是很有帮助的,可以提高电子制造业防静电管控的智慧化水平。

医用电气设备静电放电(ESD)抗扰度试验分析

本文介绍了静电放电(ESD)的形成机理、放电模型以及耦合方式,创新性地从静电放电(ESD)耦合路径入手,对静电放电(ESD)的干扰机理和抑制对策进行研究。根据电磁兼容(EMC)中静电放电(ESD)的理论研究和试验方法,针对耦合路径设计整改对策,确保整改对策的有效性和可复现性,以此提高静电放电(ESD)整改成功率。

基于ANSI/ESD S541的ESDS电子产品包装材料及其应用研究

ANSI/ESD S541—2019标准适用于静电放电敏感(ESDS)物品防护的包装材料,是保证ESDS电子产品在生产和销售的所有阶段中的储存、运输和防护的重要手段。标准提出了一种基于包装材料特性分类的防护包装技术要求和包装应用要求。就ANSI/ESD S541—2019标准中提出的ESDS电子产品包装应用要求、包装材料分类、测试方法和包装技术等展开论述,并对当前防护包材的应用实践作以介绍,对提高电子产品稳定性和可靠性具有重要价值。

A novel diode string triggered gated-Pi N junction device for electrostatic discharge protection in 65-nm CMOS technology

A novel diode string-triggered gated-Pi N junction device, which is fabricated in a standard 65-nm complementary metal-oxide semiconductor（CMOS） technology, is proposed in this paper. An embedded gated-Pi N junction structure is employed to reduce the diode string leakage current to 13 n A/μm in a temperature range from 25°C to 85°C. To provide the effective electrostatic discharge（ESD） protection in multi-voltage power supply, the triggering voltage of the novel device can be adjusted through redistributing parasitic resistance instead of changing the stacked diode number.

Structure-dependent behaviors of diode-triggered silicon controlled rectifier under electrostatic discharge stress

The comprehensive understanding of the structure-dependent electrostatic discharge behaviors in a conventional diode-triggered silicon controlled rectifier （DTSCR） is presented in this paper. Combined with the device simulation, a mathematical model is built to get a more in-depth insight into this phenomenon. The theoretical studies are verified by the transmission-line-pulsing （TLP） test results of the modified DTSCR structure, which is realized in a 65-nm complementary metal-oxide-semiconductor （CMOS） process. The detailed analysis of the physical mechanism is used to provide predictions as the DTSCR-based protection scheme is required. In addition, a method is also presented to achieve the tradeoff between the leakage and trigger voltage in DTSCR.

Measurements of Characteristics of Electromagnetic Radiation Caused by Electrostatic Discharges in Metal Sphere Gap at Voltages Less than 1 kV

In this study,the characteristics of Electromagnetic(EM) radiation caused by Electrostatic Discharges(ESDs) from metal spheres charged to voltages less than 1 kV are examined experimentally.Our experimental system consists of a pair of spherical electrodes of different diameters,a 1-18 GHz-bandwidth horn antenna and a 20-GHz-bandwidth digitizing oscilloscope.Polarization,waveform duration and peaks of antenna-received voltages from the EM field radiation are measured in order to clarify the EM radiation mechanism.The ratio of the received voltages between the antenna arrangements of the field polarization parallel and perpendicular to the spark pass is 18 to 20 dB.The polarities of the antenna-received voltages are the same as those of the charge voltages across the gap.Moreover,the waveform duration and the first peaks increase with an increase in the diameters of the spherical electrodes.Consequently,we find that the polarization,waveform duration and first peaks of the EM field radiation can be explained by a dipole antenna structure,which makes the spark part of the spherical electrodes a feeding point on the straight line passing through the centres of the two spheres.

Electrostatic Discharge Effects on the High-voltage Solar Array

A certain number of charges are deposited on the surface of high-voltage solar array because of effects of space plasma,high-energy charged particles,and solar illumination,hence the surface is charged.Phenomena of electrostatic discharge(ESD) occur on the surface when the deposited charges exceed a threshold amount.In this paper,the mechanism of this ESD is discussed.The ground simulation experiment of the ESD using spacecraft material under surface charging is described,and a novel ESD protecting method for high-voltage solar array,i.e.an active protecting method based on the local strong electric field array is proposed.The results show that the reversal potential gradient field between the cover surface and the substrate materials of high-voltage solar array is a triggering factor for the ESD on the array.The threshold voltage for the ESD occurring on the surface is about 500 V.The charged particles could be deflected using the electric field active protecting method,and hence the ESD on the surface is avoided even when the voltage on the conductor array increases to a certain value.These results pave the way for further developing the protecting measures for high-voltage solar arrays.

High holding voltage SCR for robust electrostatic discharge protection

A novel silicon controlled rectifier（SCR） with high holding voltage（Vh） for electrostatic discharge（ESD） protection is proposed and investigated in this paper. The proposed SCR obtains high Vhby adding a long N＋ layer（LN＋） and a long P＋ layer（LP＋）, which divide the conventional low voltage trigger silicon controlled rectifier（LVTSCR） into two SCRs（SCR1： P＋/Nwell/Pwell/N＋ and SCR2： P＋/LN＋/LP＋/N＋） with a shared emitter. Under the low ESD current（IESD）, the two SCRs are turned on at the same time to induce the first snapback with high V_h（V_（h1））. As the IESDincreases, the SCR2 will be turned off because of its low current gain. Therefore, the IESDwill flow through the longer SCR1 path, bypassing SCR2, which induces the second snapback with high V_h（V_（h2））. The anti-latch-up ability of the proposed SCR for ESD protection is proved by a dynamic TLP-like（Transmission Line Pulse-like） simulation. An optimized V_（h2） of 7.4 V with a maximum failure current（I_（t2）） of 14.7 m A/μm is obtained by the simulation.

一种新型小电容ESD箝位电路

为了解决RC触发机制在小电容条件下开启时间不足的问题,设计了一种新型ESD箝位电路。电路采用反馈和分流机制与电容组合的方法,将小电容与一个受反馈nMOS控制的分流nMOS并联。分流nMOS分流了电容的充电电流,从而延长了电路的开启时间。仿真结果显示,新提出的电路开启时间足够长且能够快速响应ESD事件,能够实现ESD保护。此外,该电路引入可调节的最小开启电压,能够有效避免快速上电条件下的误触发现象。

系统级ESD对IC的影响研究

随着电子产品复杂度的提高及高速化通讯应用场景的广泛存在,静电放电敏感性的问题日益突出,主要表现为集成电路出现的一系列软失效和硬失效现象,包括卡死、复位、重启甚至损坏等。主要研究了系统级静电放电对集成电路的影响。首先,介绍了静电放电的原理及其测试标准;其次,研究了芯片侧瞬态静电过电压的抓取方式;然后,对应用于不同电路设计的静电防护能力的优劣进行了评估并对比了芯片侧的静电干扰电压水平;最后,验证分析了USB接口不同的接地设计方式和静电放电施加方式对集成电路甚至系统的影响。

整车静电放电ESD测试问题分析整改

整车在进行静电放电测试过程中出现仪表报错,车辆无法正常启动现象,通过对整车控制器的逐一排查以及对静电放电路径的分析,最终发现是某个控制模块通信芯片损坏,从而导致了整车通信异常,车辆无法正常启动,最终在其PCB板上增加ESD防护进行问题规避,从而符合整车静电放电性能要求,提升了车辆的可靠性。

Ni-Cr薄膜换能组件静电响应特性与发火概率预测研究

针对电火工品在静电放电影响下可能发生误发火的问题,以Ni-Cr薄膜换能组件为研究对象,提出了一种分析其在人体静电放电下的响应特性,并预测发火概率的方法。首先,介绍了Ni-Cr薄膜换能组件系统架构,并建立了电火工品静电放电等效电路模型;其次,研究了Ni-Cr薄膜换能组件静电放电响应特性,分析了换能组件尺寸和放电电压对薄膜桥区温度的影响规律;最后,构建了Ni-Cr薄膜换能组件在统计特征下的输入条件,确定了换能组件失效判据,进而结合发火感度试验与数理统计方法,实现了在静电放电条件下电火工品发火概率的预测。研究结果表明:预测发火概率与试验值误差不超过5%,验证了本文方法的有效性。