Dynamic electrostatic-discharge path investigation relied on different impact energies in metal-oxide-semiconductor circuits

Gate-grounded n-channel metal-oxide-semiconductor(GGNMOS)devices have been widely implemented as power clamps to protect semiconductor devices from electrostatic discharge stress owing to their simple construction,easy triggering,and low power dissipation.We present a novel I-V characterization of the GGNMOS used as the power clamp in complementary metal-oxide-semiconductor circuits as a result of switching the ESD paths under different impact energies.This special effect could cause an unexpected latch-up or pre-failure phenomenon in some applications with relatively large capacitances from power supply to power ground,and thus should be urgently analyzed and resolved.Transmission-linepulse,human-body-modal,and light-emission tests were performed to explore the root cause.

Enhancement of holding voltage by a modified low-voltage trigger silicon-controlled rectifier structure for electrostatic discharge protection

A novel structure of low-voltage trigger silicon-controlled rectifiers(LVTSCRs) with low trigger voltage and high holding voltage is proposed for electrostatic discharge(ESD) protection. The proposed ESD protection device possesses an ESD implant and a floating structure. This improvement enhances the current discharge capability of the gate-grounded NMOS and weakens the current gain of the silicon-controlled rectifier current path. According to the simulation results, the proposed device retains a low trigger voltage characteristic of LVTSCRs and simultaneously increases the holding voltage to 5.53 V, providing an effective way to meet the ESD protection requirement of the 5 V CMOS process.

高压GGNMOS器件结构及工艺对ESD防护特性的影响

基于高压CMOS工艺,对高压栅极接地N型金属氧化物半导体(Highvoltagegrounded-gate N-metal-oxide-semiconductor, HV-GGNMOS)的静电放电(Electrostatic discharge, ESD)防护性能进行研究。由于强折回特性以及失效电流低,HV-GGNMOS在实际应用中受到限制。本文通过计算机辅助设计技术仿真及传输线脉冲实验研究了工艺参数及版图结构对器件ESD防护性能的影响。结果表明,增加漂移区掺杂浓度可以有效提高器件失效电流;加强体接触和增加漂移区长度可以提高器件的维持电压,但失效电流会有所下降,占用版图面积也会更大。

Enhanced gated-diode-triggered silicon-controlled rectifier for robust electrostatic discharge (ESD) protection applications

A robust electron device called the enhanced gated-diode-triggered silicon-controlled rectifier (EGDTSCR) for electrostatic discharge (ESD) protection applications has been proposed and implemented in a 0.18-μm 5-V/24-V BCD process. The proposed EGDTSCR is constructed by adding two gated diodes into a conventional ESD device called the modified lateral silicon-controlled rectifier (MLSCR). With the shunting effect of the surface gated diode path, the proposed EGDTSCR, with a width of 50 μm, exhibits a higher failure current (i.e., 3.82 A) as well as a higher holding voltage (i.e., 10.21 V) than the MLSCR.

Study on electrostatic discharge(ESD)characteristics of ultra-thin dielectric film

Electrostatic discharge(ESD)event usually destroys the electrical properties of dielectric films,resulting in product failure.In this work,the breakdown characteristic of machine mode(MM)ESD on three different nano size films of head gimble assemble are obtained experimentally.The breakdown voltage and thickness parameters show a positive proportional relationship,but they are generally very low and have large discrete characteristics(~30%).The maximum and minimum breakdown voltages of the tested samples are 1.08 V and 0.46 V,which are far lower than the requirement of the current standard(25 V).In addition,the judgment criterion of product damage is given,and the relationship between discharge voltage polarity,initial resistance and breakdown voltage is studied.Finally,the theoretical analysis of the breakdown characteristic law has been given.

基于工业数据挖掘的ESD软失效分析

针对电子产品出货后出现ESD软失效而导致的退货现象,文章通过机器学习算法分析产品ICT电性能测试参数、生产线ESD防护监控数据和产品ESD软失效的相关性。集成算法模型经过优化,分类准确率达到0.88,可以用于量产电子产品的ESD软失效的识别和出货风险管控。同时,利用ESD防护监控点风险指数数据集可以提高产品ESD软失效的识别准确率(8.6%)。安装部署基于物联网技术的静电放电防护监控系统,对管控电子产品生产过程中的ESD软失效风险以及控制出货风险是很有帮助的,可以提高电子制造业防静电管控的智慧化水平。

医用电气设备静电放电(ESD)抗扰度试验分析

本文介绍了静电放电(ESD)的形成机理、放电模型以及耦合方式,创新性地从静电放电(ESD)耦合路径入手,对静电放电(ESD)的干扰机理和抑制对策进行研究。根据电磁兼容(EMC)中静电放电(ESD)的理论研究和试验方法,针对耦合路径设计整改对策,确保整改对策的有效性和可复现性,以此提高静电放电(ESD)整改成功率。

基于ANSI/ESD S541的ESDS电子产品包装材料及其应用研究

ANSI/ESD S541—2019标准适用于静电放电敏感(ESDS)物品防护的包装材料,是保证ESDS电子产品在生产和销售的所有阶段中的储存、运输和防护的重要手段。标准提出了一种基于包装材料特性分类的防护包装技术要求和包装应用要求。就ANSI/ESD S541—2019标准中提出的ESDS电子产品包装应用要求、包装材料分类、测试方法和包装技术等展开论述,并对当前防护包材的应用实践作以介绍,对提高电子产品稳定性和可靠性具有重要价值。

A novel diode string triggered gated-Pi N junction device for electrostatic discharge protection in 65-nm CMOS technology

A novel diode string-triggered gated-Pi N junction device, which is fabricated in a standard 65-nm complementary metal-oxide semiconductor（CMOS） technology, is proposed in this paper. An embedded gated-Pi N junction structure is employed to reduce the diode string leakage current to 13 n A/μm in a temperature range from 25°C to 85°C. To provide the effective electrostatic discharge（ESD） protection in multi-voltage power supply, the triggering voltage of the novel device can be adjusted through redistributing parasitic resistance instead of changing the stacked diode number.

Structure-dependent behaviors of diode-triggered silicon controlled rectifier under electrostatic discharge stress

The comprehensive understanding of the structure-dependent electrostatic discharge behaviors in a conventional diode-triggered silicon controlled rectifier （DTSCR） is presented in this paper. Combined with the device simulation, a mathematical model is built to get a more in-depth insight into this phenomenon. The theoretical studies are verified by the transmission-line-pulsing （TLP） test results of the modified DTSCR structure, which is realized in a 65-nm complementary metal-oxide-semiconductor （CMOS） process. The detailed analysis of the physical mechanism is used to provide predictions as the DTSCR-based protection scheme is required. In addition, a method is also presented to achieve the tradeoff between the leakage and trigger voltage in DTSCR.

Electrostatic Discharge Effects on the High-voltage Solar Array

A certain number of charges are deposited on the surface of high-voltage solar array because of effects of space plasma,high-energy charged particles,and solar illumination,hence the surface is charged.Phenomena of electrostatic discharge(ESD) occur on the surface when the deposited charges exceed a threshold amount.In this paper,the mechanism of this ESD is discussed.The ground simulation experiment of the ESD using spacecraft material under surface charging is described,and a novel ESD protecting method for high-voltage solar array,i.e.an active protecting method based on the local strong electric field array is proposed.The results show that the reversal potential gradient field between the cover surface and the substrate materials of high-voltage solar array is a triggering factor for the ESD on the array.The threshold voltage for the ESD occurring on the surface is about 500 V.The charged particles could be deflected using the electric field active protecting method,and hence the ESD on the surface is avoided even when the voltage on the conductor array increases to a certain value.These results pave the way for further developing the protecting measures for high-voltage solar arrays.

High holding voltage SCR for robust electrostatic discharge protection

A novel silicon controlled rectifier（SCR） with high holding voltage（Vh） for electrostatic discharge（ESD） protection is proposed and investigated in this paper. The proposed SCR obtains high Vhby adding a long N＋ layer（LN＋） and a long P＋ layer（LP＋）, which divide the conventional low voltage trigger silicon controlled rectifier（LVTSCR） into two SCRs（SCR1： P＋/Nwell/Pwell/N＋ and SCR2： P＋/LN＋/LP＋/N＋） with a shared emitter. Under the low ESD current（IESD）, the two SCRs are turned on at the same time to induce the first snapback with high V_h（V_（h1））. As the IESDincreases, the SCR2 will be turned off because of its low current gain. Therefore, the IESDwill flow through the longer SCR1 path, bypassing SCR2, which induces the second snapback with high V_h（V_（h2））. The anti-latch-up ability of the proposed SCR for ESD protection is proved by a dynamic TLP-like（Transmission Line Pulse-like） simulation. An optimized V_（h2） of 7.4 V with a maximum failure current（I_（t2）） of 14.7 m A/μm is obtained by the simulation.

一种新型小电容ESD箝位电路

为了解决RC触发机制在小电容条件下开启时间不足的问题,设计了一种新型ESD箝位电路。电路采用反馈和分流机制与电容组合的方法,将小电容与一个受反馈nMOS控制的分流nMOS并联。分流nMOS分流了电容的充电电流,从而延长了电路的开启时间。仿真结果显示,新提出的电路开启时间足够长且能够快速响应ESD事件,能够实现ESD保护。此外,该电路引入可调节的最小开启电压,能够有效避免快速上电条件下的误触发现象。

系统级ESD对IC的影响研究

随着电子产品复杂度的提高及高速化通讯应用场景的广泛存在,静电放电敏感性的问题日益突出,主要表现为集成电路出现的一系列软失效和硬失效现象,包括卡死、复位、重启甚至损坏等。主要研究了系统级静电放电对集成电路的影响。首先,介绍了静电放电的原理及其测试标准;其次,研究了芯片侧瞬态静电过电压的抓取方式;然后,对应用于不同电路设计的静电防护能力的优劣进行了评估并对比了芯片侧的静电干扰电压水平;最后,验证分析了USB接口不同的接地设计方式和静电放电施加方式对集成电路甚至系统的影响。

整车静电放电ESD测试问题分析整改

整车在进行静电放电测试过程中出现仪表报错,车辆无法正常启动现象,通过对整车控制器的逐一排查以及对静电放电路径的分析,最终发现是某个控制模块通信芯片损坏,从而导致了整车通信异常,车辆无法正常启动,最终在其PCB板上增加ESD防护进行问题规避,从而符合整车静电放电性能要求,提升了车辆的可靠性。

基于高分子电压诱导变阻膜的全PCB抗脉冲防护

随着芯片集成度的不断提高,内部互连导线间距越来越小,器件更易在静电作用下受到损害。为提高印制电路板(PCB)在实际应用中抗静电放电(ESD)和电磁脉冲(EMP)的能力,制作了一种高分子电压诱导变阻膜,将其嵌入PCB中形成脉冲吸收网络,使全板具备抗瞬变脉冲能力,实现对ESD和EMP的全系统防护。ESD防护实测结果表明,对比普通PCB,全抗脉冲PCB对静电脉冲有更快的响应速度和更高的释放效率;传输线脉冲(TLP)测试结果表明,采用电压诱导变阻膜的PCB中每一点都具有过电压脉冲吸收能力,电流泄放能力可达50 A以上。

一种新的BMM-ESD电流解析式计算方法

为进一步发展BMM-ESP电流的电路建模求解法,分析了静电放电测试环境在实际放电测试过程中的寄生参量并建立了一个9元件ESD电路模型,求得了电流在复频域的表达式,进而通过拉普拉斯反变换解得了BMM-ESD电流时域解析式。计算验证了实测BMM-ESD电流复频域表达式极点分布的规律:共6个极点都位于复频域的左半平面,含2对共轭复数和2个实数,从而概括出BMM-ESD电流时域解析式的一般形式。算例表明,电流解析式符合IEC规定,吻合实测波形,尤其能够有效描述实际ESD波形中常见的非标准现象:位于第1峰值与第2峰值间的寄生振荡。

ESD发生器开关动作对抗扰度试验的影响

分析了人体-金属静电放电(ESD)发生器开关动作的基本过程;说明了在ESD抗扰度试验中ESD发生器开关动作的影响。通过空气放电模拟测试装置测量并记录了ESS-200 AX、SANKI NS61000-2A和NSG-435 3种ESD发生器开关动作的影响。由小环耦合电压的测量研究了ESD发生器开关动作产生的辐射场。结果表明,使用不同的ESD发生器开关动作的影响程度不一样,且使用相同的ESD发生器开关闭合和开关释放的影响存在差异。对小环耦合电压的频谱分析表明,开关动作会产生频谱范围较宽的电磁骚扰,影响对高速逻辑器件的ESD抗扰度试验。在进行ESD抗扰度试验时,需考虑ESD辐射场,尤其需要降低或控制ESD发生器开关动作产生的辐射场。

ESD辐射场的计算及对传输线的耦合研究

为分析静电放电的辐射场及其对传输线与负载终端的影响,采用了一种基于脉冲函数的静电放电电流波形解析表达式计算了静电放电电磁脉冲辐射场并给出了近场和远场波形。结果表明放电电场包括由初始电荷引起的静电场和由放电电流引起的辐射场,在放电电极附近,静电场远大于辐射场,但静电场随空间距离衰减得很快,在远区场主要由放电电流引起的辐射场。利用传输线理论建立静电放电场对电长导线的耦合计算模型得出了静电放电辐射场在线上的感应电压和感应电流计算方程。

高频小功率硅双极器件ESD潜在失效的无损检测方法

目前国内外研究人员多集中于研究MOS器件和GaAs器件的静电放电(ESD)潜在性失效,而对高频小功率硅双极晶体管的静电放电潜在性失效则研究较少。为此,参考国内外研究人员的研究结果,选择采用高温反偏法、低频噪声法以及电参数测量法来对高频小功率硅双极晶体管静电放电潜在性失效的无损检测方法进行了较为细致的分析研究。通过详细比较后可以确定,高温反偏法和低频噪声法均不能用来检测高频小功率硅双极晶体管的静电放电失效,也就更不能用来检测判别此类器件的静电放电潜在性失效。最后,通过对多个电参数的测量与对比发现,高频小功率硅双极晶体管集电极-基极反偏结漏电流的大范围变化可以表征此类器件静电放电潜在性失效的存在。