期刊文献+
共找到1篇文章
< 1 >
每页显示 20 50 100
A write buffer design based on stable and area-saving embedded SRAM for flash applications
1
作者 CAO Hua Min HUO Zong Liang +7 位作者 WANG Yu LI Ting LIU Jing JIN Lei JIANG Dan-Dan ZHANG Deng Jun LI Di LIU Ming 《Science China(Technological Sciences)》 SCIE EI CAS CSCD 2015年第2期357-361,共5页
This paper presents an embedded SRAM design for write buffer applications in flash memories.The write buffer is implemented with a newly proposed self-adaptive timing control circuit,an area-saving sense-latch circuit... This paper presents an embedded SRAM design for write buffer applications in flash memories.The write buffer is implemented with a newly proposed self-adaptive timing control circuit,an area-saving sense-latch circuit and 6 T SRAM cell units.A 2 kb SRAM macro with the area of 135μm×180μm is implemented in and applied to a 128 Mb NOR flash memory with the SMIC 65 nm NOR flash memory process.Both simulation and chip test results show that the SRAM write buffer is beneficial to high-density flash memory design. 展开更多
关键词 write buffer embedded sram FLASH 65 nm technology 2 kb 128 Mb
原文传递
上一页 1 下一页 到第
使用帮助 返回顶部