Secure encryption embedded processor design for wireless sensor network application

This paper presents a new encryption embedded processor aimed at the application requirement of wireless sensor network （WSN）. The new encryption embedded processor not only offers Rivest Shamir Adlemen （RSA）, Advanced Encryption Standard （AES）, 3 Data Encryption Standard （3 DES） and Secure Hash Algorithm 1 （SHA - 1 ） security engines, but also involves a new memory encryption scheme. The new memory encryption scheme is implemented by a memory encryption cache （MEC）, which protects the confidentiality of the memory by AES encryption. The experi- ments show that the new secure design only causes 1.9% additional delay on the critical path and cuts 25.7% power consumption when the processor writes data back. The new processor balances the performance overhead, the power consumption and the security and fully meets the wireless sensor environment requirement. After physical design, the new encryption embedded processor has been successfully tape-out.

PEM:a lightweight program memory encryption mechanism for embedded processor

Application of embedded systems is faced with multiple threats against security. To solve this problem, this article proposes a new program memory encryption mechanism （PEM） to enhance the security of embedded processor. The new mechanism encrypts all the programs via a secure cache structure. It not only caches the instructions read from the off-chip memory, but also stores the pad values used to encrypt the plaintext. It effectively accelerates encryption and reduces the performance overhead. Besides the encryption, PEM also monitors the program modifications and reset behaviors to reduce the risk of vicious tamper. The experiment indicates that PEM has an average of 2.3 % performance improvement and results in a 25.71% power reduction in the write-back stage. The new scheme offers a good balance between performance and security. It is fully practicable for embedded processor.

Multi-bit upset aware hybrid error-correction for cache in embedded processors

For the processor working in the radiation environment in space, it tends to suffer from the single event effect on circuits and system failures, due to cosmic rays and high energy particle radiation. Therefore, the reliability of the processor has become an increasingly serious issue. The BCH-based error correction code can correct multibit errors, but it introduces large latency overhead. This paper proposes a hybrid error correction approach that combines BCH and EDAC to correct both multi-bit and single-bit errors for caches with low cost. The proposed technique can correct up to four-bit error, and correct single-bit error in one cycle. Evaluation results show that, the proposed hybrid error-correction scheme can improve the performance of cache accesses up to 20% compared to the pure BCH scheme.

RV16:An Ultra-Low-Cost Embedded RISC-V Processor Core

Embedded and Internet of Things(IoT)devices have extremely strict requirements on the area and power consumption of the processor because of the limitation on its working environment.To reduce the overhead of the embedded processor as much as possible,this paper designs and implements a configurable 32-bit in-order RISC-V processor core based on the 16-bit data path and units,named RV16.The evaluation results show that,compared with the traditional 32-bit RISC-V processor with similar features,RV16 consumes fewer hardware resources and less power consumption.The maximum performance of RV16 running Dhrystone and CoreMark benchmarks is 0.92 DMIPS/MHz and 1.51 CoreMark/MHz,respectively,reaching 75%and 71%of traditional 32-bit processors,respectively.Moreover,a properly configured RV16 running program also consumes less energy than a traditional 32-bit processor.

Embedding Binary Tree in VLSI/WSI Processor Array

Many reconfiguration schemes for fault-tolerant binary tree architectures have been proposed in the lite..t.re[1-6]. The VLSI layouts of most previous studies are based on the classical H-tree layout, resulting in low area utilization and likely an unnecessarily high manufacturing cost simply due to the waste of a significaot portion of silicon area. In this paper, we present an area-efficient approach to the reconfigurable binary tree architecture. Area utilization and interconnection complexity of our design compare favorably with the other known approaches. In the reliability analysis, we take ioto arcount the faCt that accepted chips (after fabrication) are with dmereot degrees of redundancy initially, so as to obtain results which better reflect real situations.

Developing a power monitoring and protection system for the junction boxes of an experimental seafloor observatory network

A power monitoring and protection system based on an embedded processor was designed for the junction boxes(JBs) of an experimental seafloor observatory network in China. The system exhibits high reliability, fast response, and high real-time performance. A two-step power management method which uses metal-oxide-semiconductor field-effect transistors(MOSFETs) and a mechanical contactor in series was adopted to generate a reliable power switch, to limit surge currents and to facilitate automatic protection. Grounding fault diagnosis and environmental monitoring were conducted by designing a grounding fault detection circuit and by using selected sensors, respectively. The data collected from the JBs must be time-stamped for analysis and for correlation with other events and data. A highly precise system time, which is necessary for synchronizing the times within and across nodes, was generated through the IEEE 1588(precision clock synchronization protocol for networked measurement and control systems) time synchronization method. In this method, time packets were exchanged between the grandmaster clock at the shore station and the slave clock module of the system. All the sections were verified individually in the laboratory prior to a sea trial. Finally, a subsystem for power monitoring and protection was integrated into the complete node system, installed in a frame, and deployed in the South China Sea. Results of the laboratory and sea trial experiments demonstrated that the developed system was effective, stable, reliable, and suitable for continuous deep-sea operation.

A Power-Aware Branch Predictor by Accessing the BTB Selectively

Microarchitects should consider power consumption, together with accuracy, when designing a branch predictor, especially in embedded processors. This paper proposes a power-aware branch predictor, which is based on the gshare predictor, by accessing the BTB （Branch Target Buffer） selectively. To enable the selective access to the BTB, the PHT （Pattern History Table） in the proposed branch predictor is accessed one cycle earlier than the traditional PHT if the program is executed sequentially without branch instructions. As a side effect, two predictions from the PHT are obtained through one access to the PHT, resulting in more power savings. In the proposed branch predictor, if the previous instruction was not a branch and the prediction from the PHT is untaken, the BTB is not accessed to reduce power consumption. If the previous instruction was a branch, the BTB is always accessed, regardless of the prediction from the PHT, to prevent the additional delay/accuracy decrease. The proposed branch predictor reduces the power consumption with little hardware overhead, not incurring additional delay and never harming prediction accuracy. The simulation results show that the proposed branch predictor reduces the power consumption by 29-47%.

Space time clock:An on-chip clock with 10^(-12) instability

High precision and stable clock is extremely important in communication and navigation.The miniaturization of the clocks is considered to be the trend to satisfy the demand for5G and the next generation communications.Based on the concept of meter bar and the principle of the constancy of light velocity,we designed a micro clock,Space Time Clock(STC),with the size smaller than 1 mm×1 mm and the power dissipation less than 2 m W.Designed in integrated circuit of 0.18μm technology,the instability of STC is assessed to be 2.23×10^(-12)and the trend of the instability is reversely proportional toτ.With the potential ability to reach the level of 10instability on chip in the future,the period of the STC’s signal is locked on the delay time defined by the meter bar which keeps the time reference constant.Because of its superior performance,the STC is more suitable for mobile communication,PNT(Positioning,Navigation and Timing),embedded processor and deep space application,and becomes the main payload of the ASRTU satellite scheduled to launch next year and investigate in space environment.