An extremely low power voltage reference without resistors is presented for power-aware ASICs. In order to reduce the power dissipation, an Oguey current reference source is used to reduce the static current; a cascod...An extremely low power voltage reference without resistors is presented for power-aware ASICs. In order to reduce the power dissipation, an Oguey current reference source is used to reduce the static current; a cascode current mirror is used to increase the power supply rejection ratio (PSRR) and reduce the line sensitivity of the circuit. The voltage reference is fabricated in SMIC 0.18μm CMOS process. The measured results for the voltage reference demonstrate that the temperature coefficient of the voltage is 66 ppm/℃ in a range from 25 to 100 ℃. The line sensitivity is 0.9% in a supply voltage range of 1.8 to 3,3 V, and PSRR is -49 dB at 100 Hz. The power dissipation is 200 nW. The chip area is 0.01 mm2. The circuit can be used as an elementary circuit block for power-aware ASICs.展开更多
基金Project supported by the National Natural Science Foundation of China(Nos.61161003,61264001,61166004)the Guangxi Natural Science Foundation(No.2013GXNSFAA019333)
文摘An extremely low power voltage reference without resistors is presented for power-aware ASICs. In order to reduce the power dissipation, an Oguey current reference source is used to reduce the static current; a cascode current mirror is used to increase the power supply rejection ratio (PSRR) and reduce the line sensitivity of the circuit. The voltage reference is fabricated in SMIC 0.18μm CMOS process. The measured results for the voltage reference demonstrate that the temperature coefficient of the voltage is 66 ppm/℃ in a range from 25 to 100 ℃. The line sensitivity is 0.9% in a supply voltage range of 1.8 to 3,3 V, and PSRR is -49 dB at 100 Hz. The power dissipation is 200 nW. The chip area is 0.01 mm2. The circuit can be used as an elementary circuit block for power-aware ASICs.
文摘提出一种新的锁频环(FLL)鉴别器设计思路.在回波信号多普勒变化率较小的前提下,将正交解调后的差信号视为线性调频(LFM)信号,同时提取其起始频率和频率变化率作为FLL误差控制量,增强了FLL容忍高动态信号的能力.FFT鉴别算法和点积叉积鉴频算法在频率跟踪的不同阶段相互配合构成鉴别器,既获得了宽的鉴别范围又获得了高的鉴别精度.针对极低信噪比情况下偶发鉴别野值的问题,提出了行之有效且实现简单的野值识别与剔除算法.仿真结果表明上述思路可行,采用该鉴别器的FLL在信噪比低至-40 dB时能够容忍较高动态变化,且频率跟踪精度达0.2 Hz.