This paper shows that the 8-problem for holomorphic (0, 2)-forms on Hubert spaces is solv-able on pseudoconvex open subsets. By using this result, the authors investigate the existence of the solution of the -equation...This paper shows that the 8-problem for holomorphic (0, 2)-forms on Hubert spaces is solv-able on pseudoconvex open subsets. By using this result, the authors investigate the existence of the solution of the -equation for holomorphic (0, 2)-forms on pseudoconvex domains in D.F.N. spaces.展开更多
A novel flash memory cell with stacked structure （Si substrate/SiGe quantum dots/tunneling oxide/polySi floating gate） is proposed and demonstrated to achieve enhanced F-N tunneling for both programming and erasing....A novel flash memory cell with stacked structure （Si substrate/SiGe quantum dots/tunneling oxide/polySi floating gate） is proposed and demonstrated to achieve enhanced F-N tunneling for both programming and erasing. Simulation results indicate the new structure provides high speed and reliability. Experimental results show that the operation voltage can be as much as 4V less than that of conventional full F-N tunneling NAND memory cells. Memory cells with the proposed structure can achieve higher speed, lower voltage, and higher reliability.展开更多
基金The first author was supported by KOSEF postdoctoral fellowship 1998 and the second author was supported by the Brain Korea 21 P
文摘This paper shows that the 8-problem for holomorphic (0, 2)-forms on Hubert spaces is solv-able on pseudoconvex open subsets. By using this result, the authors investigate the existence of the solution of the -equation for holomorphic (0, 2)-forms on pseudoconvex domains in D.F.N. spaces.
文摘A novel flash memory cell with stacked structure （Si substrate/SiGe quantum dots/tunneling oxide/polySi floating gate） is proposed and demonstrated to achieve enhanced F-N tunneling for both programming and erasing. Simulation results indicate the new structure provides high speed and reliability. Experimental results show that the operation voltage can be as much as 4V less than that of conventional full F-N tunneling NAND memory cells. Memory cells with the proposed structure can achieve higher speed, lower voltage, and higher reliability.
