Temperature-insensitive reading of a flash memory cell

The temperature characteristics of the read current of the NOR embedded flash memory with a 1.5T-per-cell structure are theoretically analyzed and experimentally verified.We verify that for a cell programmed with a“10”state,the read current is either increasing,decreasing,or invariable with the temperature,essentially depending on the reading overdrive voltage of the selected bitcell,or its programming strength.By precisely controlling the programming strength and thus manipulating its temperature coefficient,we propose a new setting method for the reference cells that programs each of reference cells to a charge state with a temperature coefficient closely tracking tail data cells,thereby solving the current coefficient mismatch and improving the read window.

Novel p-Channel Selected n-Channel Divided Bit-Line NOR Flash Memory Using Source Induced Band-to-Band Hot Electron Injection Programming

A novel p-channel selected n-channel divided bit-line NOR(PNOR) flash memory,which features low programming current,low power,high access current,and slight bit-line disturbance,is proposed.By using the source induced band-to-band hot electron injection (SIBE) to perform programming and dividing the bit-line to the sub-bit-lines,the programming current and power can be reduced to 3.5μA and 16.5μW with the sub-bit-line width equaling to 128,and a read current of 60μA is obtained.Furthermore,the bit-line disturbance is also significantly alleviated.

A Novel Flash Memory Using Band-to-Band Tunneling Induced Hot Electron Injection to Program

A novel band to band hot electron programming flash memory device,which features programming with high speed,low voltage,low power consumption,large read current and short access time,is proposed.The new memory cell is programmed by band to band tunneling induced hot electron (BBHE) injection method at the drain,and erased by Fowler Nordheim tunneling through the source region.The work shows that the programming control gate voltage can be reduced to 8V,and the drain leakage current is only 3μA/μm.Under the proposed operating conditions,the program efficiency and the read current rise up to 4×10 -4 and 60μA/μm,respectively,and the program time can be as short as 16μs

Low Voltage Flash Memory Cells Using SiGe Quantum Dots for Enhancing F-N Tunneling

A novel flash memory cell with stacked structure （Si substrate/SiGe quantum dots/tunneling oxide/polySi floating gate） is proposed and demonstrated to achieve enhanced F-N tunneling for both programming and erasing. Simulation results indicate the new structure provides high speed and reliability. Experimental results show that the operation voltage can be as much as 4V less than that of conventional full F-N tunneling NAND memory cells. Memory cells with the proposed structure can achieve higher speed, lower voltage, and higher reliability.

A Novel Non-Planar Cell Structure for Flash Memory

Proposed herein is a novel non planar cell structure for flash memory which has been fabricated to achieve high programming speed with low operating voltage.This memory cell preserves a simple stacked gate structure which only requires an additional masking step to form the novel structure in the channel.For the cell of the 1 2μm gate length,the programming speed of 43μs under the measuring condition of V g=15V, V d=5V,and the erasing time of 24ms under V g=-5V, V s=8V are obtained.The programming speed is faster than that of the conventional planar cell structure.This superior programming speed makes it suitable for high speed application.

SCDI Flash Memory Device Ⅰ: Simulation and Analysis

Step channel direct injection(SCDI)flash memory device which had been developed changes the hot carrier injection method by making a shallow step in the middle of channel .Therefore high speed for programming,high efficiency for injection,and lower working voltage are obtained.Simulation and analysis for the proposed SCDI structure device are done and an optimization scheme to improve the utmost performance of SCDI device is given...

SCDI Flash Memory Device Ⅱ:Experiments and Characteristics

Step channel direct injection(SCDI) flash memory device is successfully achieved by 1 2μm CMOS technology,moreover good performance is obtained.At the bias condition of V g=6V, V d=5V,the programming speed of SCDI device is 42μs.Under the condition of V g=-8V, V s=8V,the erasing speed is 24ms.Compared with the same size of conventional flash memory device whose corresponding parameters are 500μs and 24ms,respectively,the performance of SCDI device is remarkably improved.During manufacturing of SCDI device,the key technologies are to make the shallow step with appropriate depth and angle,along with eliminating the etch damage during the process of Si 3N 4 spacer.

Heavy ion induced upset errors in 90-nm 64 Mb NOR-type floating-gate Flash memory

Upset errors in 90-nm 64 Mb NOR-type floating-gate Flash memory induced by accelerated ^（129）Xe and ^（209）Bi ions are investigated in detail. The linear energy transfer covers the range from 50 to 99.8 Me V/（mg/cm^2）. When the memory chips are powered off during heavy ions irradiation, single-event-latch-up and single-event-function-interruption are excluded,and only 0-〉1 upset errors in the memory array are observed. These error bit rates seem very difficult to achieve and cannot be simply recovered based on the power cycle. The number of error bits shows a strong dependence on the linear energy transfer（LET）. Under room-temperature annealing conditions, the upset errors can be reduced by about two orders of magnitude using rewrite/reprogram operations, but they subsequently increase once again in a few minutes after the power cycle. High-temperature annealing can diminish almost all error bits, which are affected by the lower LET ^（129）Xe ions. The percolation path between the floating-gate（FG） and the substrate contributes to the radiation-induced leakage current, and has been identified as the root cause of the upset errors of the Flash memory array in this work.

Low-Complexity Detection and Decoding Scheme for LDPC-Coded MLC NAND Flash Memory

With the development of manufacture technology, the multi-level cell(MLC)technique dramatically increases the storage density of NAND flash memory. As the result,cell-to-cell interference(CCI) becomes more serious and hence causes an increase in the raw bit error rate of data stored in the cells.Recently, low-density parity-check(LDPC)codes have appeared to be a promising solution to combat the interference of MLC NAND flash memory. However, the decoding complexity of the sum-product algorithm(SPA) is extremely high. In this paper, to improve the accuracy of the log likelihood ratio(LLR) information of each bit in each NAND flash memory cell, we adopt a non-uniform detection(N-UD) which uses the average maximum mutual information to determine the value of the soft-decision reference voltages.Furthermore, with an aim to reduce the decoding complexity and improve the decoding performance, we propose a modified soft reliabilitybased iterative majority-logic decoding(MSRBI-MLGD) algorithm, which uses a non-uniform quantizer based on power function to decode LDPC codes. Simulation results show that our design can offer a desirable trade-off between the performance and complexity for high-column-weight LDPC-coded MLC NAND flash memory.

LDPC Coding Scheme for Improving the Reliability of Multi-Level-Cell NAND Flash Memory in Radiation Environments

Utilizing commercial off-the-shelf(COTS) components in satellites has received much attention due to the low cost. However, commercial memories suffer severe reliability problems in radiation environments. This paper studies the low-density parity-check(LDPC) coding scheme for improving the reliability of multi-level-cell(MLC) NAND Flash memory in radiation environments. Firstly, based on existing physical experiment works, we introduce a new error model for heavyion irradiations; secondly, we explore the optimization of writing voltage allocation to maximize the capacity of the storage channel; thirdly, we design the degree distribution of LDPC codes that is specially suitable for the proposed model; finally, we propose a joint detection-decoding scheme based on LDPC codes, which estimates the storage channel state and executes an adaptive log-likelihood ratio(LLR) calculation to achieve better performance. Simulation results show that, compared with the conventional LDPC coding scheme, the proposed scheme may almost double the lifetime of the MLC NAND Flash memory in radiation environments.

Random telegraph noise on the threshold voltage of multi-level flash memory

We investigate the impact of random telegraph noise（RTN） on the threshold voltage of multi-level NOR flash memory.It is found that the threshold voltage variation（？Vth） and the distribution due to RTN increase with the programmed level（Vth） of flash cells. The gate voltage dependence of RTN amplitude and the variability of RTN time constants suggest that the large RTN amplitude and distribution at the high program level is attributed to the charge trapping in the tunneling oxide layer induced by the high programming voltages. A three-dimensional TCAD simulation based on a percolation path model further reveals the contribution of those trapped charges to the threshold voltage variation and distribution in flash memory.

Program Error Mitigation in MLC NAND Flash Memory with Soft Decision Decoders

Benefiting from strong decoding capabilities,soft-decision decoding has been used to replace hard-decision decoding in various communication systems,and NAND flash memory systems are no exception.However,soft-decision decoding relies heavily on accurate soft information.Owing to the incremental step pulse programming(ISPP),program errors(PEs)in multi-level cell(MLC)NAND flash memory have different characteristics compared to other types of errors,which is very difficult to obtain such accurate soft information.Therefore,the characteristics of the log-likelihood ratio(LLR)of PEs are investigated first in this paper.Accordingly,a PE-aware statistical method is proposed to determine the usage of PE mitigation schemes.In order to reduce the PE estimating workload of the controller,an adaptive blind clipping(ABC)scheme is proposed subsequently to approximate the PEs contaminated LLR with different decoding trials.Finally,simulation results demonstrate that(1)the proposed PE-aware statistical method is effective in practice,and(2)ABC scheme is able to provide satisfactory bit error rate(BER)and frame error rate(FER)performance in a penalty of negligible increasing of decoding latency.

Improvement of Operation Characteristics for MONOS Charge Trapping Flash Memory with SiGe Buried Channel

We propose and investigate a novel metal/SiO_2/Si_3N_4/SiO_2/SiGe charge trapping flash memory structure（named as MONOS）, utilizing Si Ge as the buried channel. The fabricated memory device demonstrates excellent programerasable characteristics attributed to the fact that more carriers are generated by the smaller bandgap of Si Ge during program/erase operations. A flat-band voltage shift 2.8 V can be obtained by programming at ＋11 V for 100 us. Meanwhile, the memory device exhibits a large memory window of ~7.17 V under ±12 V sweeping voltage, and a negligible charge loss of 18% after 104 s＇ retention. In addition, the leakage current density is lower than 2.52 × 10^（-7） A·cm^（-2） below a gate breakdown voltage of 12.5 V. Investigation of leakage current-voltage indicates that the Schottky emission is the predominant conduction mechanisms for leakage current. These desirable characteristics are ascribed to the higher trap density of the Si_3N_4 charge trapping layer and the better quality of the interface between the SiO_2 tunneling layer and the Si Ge buried channel. Therefore, the application of the Si Ge buried channel is very promising to construct 3 D charge trapping NAND flash devices with improved operation characteristics.

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Optimized operation scheme of flash-memory-based neural network online training with ultra-high endurance

With the rapid development of machine learning,the demand for high-efficient computing becomes more and more urgent.To break the bottleneck of the traditional Von Neumann architecture,computing-in-memory(CIM)has attracted increasing attention in recent years.In this work,to provide a feasible CIM solution for the large-scale neural networks(NN)requiring continuous weight updating in online training,a flash-based computing-in-memory with high endurance(10^(9) cycles)and ultrafast programming speed is investigated.On the one hand,the proposed programming scheme of channel hot electron injection(CHEI)and hot hole injection(HHI)demonstrate high linearity,symmetric potentiation,and a depression process,which help to improve the training speed and accuracy.On the other hand,the low-damage programming scheme and memory window(MW)optimizations can suppress cell degradation effectively with improved computing accuracy.Even after 109 cycles,the leakage current(I_(off))of cells remains sub-10pA,ensuring the large-scale computing ability of memory.Further characterizations are done on read disturb to demonstrate its robust reliabilities.By processing CIFAR-10 tasks,it is evident that~90%accuracy can be achieved after 109 cycles in both ResNet50 and VGG16 NN.Our results suggest that flash-based CIM has great potential to overcome the limitations of traditional Von Neumann architectures and enable high-performance NN online training,which pave the way for further development of artificial intelligence(AI)accelerators.

Dynamic Write-Voltage Design and Read-Voltage Optimization for MLC NAND Flash Memory

To mitigate the impact of noise and inter-ference on multi-level-cell(MLC)flash memory with the use of low-density parity-check(LDPC)codes,we propose a dynamic write-voltage design scheme con-sidering the asymmetric property of raw bit error rate(RBER),which can obtain the optimal write voltage by minimizing a cost function.In order to further improve the decoding performance of flash memory,we put forward a low-complexity entropy-based read-voltage optimization scheme,which derives the read voltages by searching for the optimal entropy value via a log-likelihood ratio(LLR)-aware cost function.Simulation results demonstrate the superiority of our proposed dynamic write-voltage design scheme and read-voltage optimization scheme with respect to the existing counterparts.

Flash-based in-memory computing for stochastic computing in image edge detection

The“memory wall”of traditional von Neumann computing systems severely restricts the efficiency of data-intensive task execution,while in-memory computing(IMC)architecture is a promising approach to breaking the bottleneck.Although variations and instability in ultra-scaled memory cells seriously degrade the calculation accuracy in IMC architectures,stochastic computing(SC)can compensate for these shortcomings due to its low sensitivity to cell disturbances.Furthermore,massive parallel computing can be processed to improve the speed and efficiency of the system.In this paper,by designing logic functions in NOR flash arrays,SC in IMC for the image edge detection is realized,demonstrating ultra-low computational complexity and power consumption(25.5 fJ/pixel at 2-bit sequence length).More impressively,the noise immunity is 6 times higher than that of the traditional binary method,showing good tolerances to cell variation and reliability degradation when implementing massive parallel computation in the array.

A novel sourceline voltage compensation circuit for embedded NOR flash memory

A novel sourceline voltage compensation circuit for program operation in embedded flash memory is presented. With the sourceline voltage compensation circuit, the charge pump can modulate the output voltage according to the number of cells to be programmed with data ＂0＂. So the IR drop on the sourceline decoding path is compensated, and a stable sourceline voltage can be obtained. In order to reduce the power dissipation in program operation, a bit-inversion program circuit is adopted. By using the bit-inversion program circuit, the cells programmed to data ＂0＂ are limited to half of the bits of a write data word, thus power dissipation in program operation is greatly reduced. A 1.8-V 8 × 64-kbits embedded NOR flash memory employing the two circuits has been integrated using a GSMC 0.18-μm 4-poly 4-metal CMOS process.

A new low-voltage and high-speed sense amplifier for flash memory

A new low-voltage and high-speed sense amplifier is presented, based on a very simple direct currentmode comparison. It adopts low-voltage reference current extraction and a dynamic output method to realize its performance indicators such as low voltage, low power and high precision. The proposed amplifier can sense a 0.5 #A current gap and work with a lowest voltage of 1 V. In addition, the current power of a single amplifier is optimized by 15%.

A low-voltage sense amplifier for high-performance embedded flash memory

This paper presents a sense amplifier scheme for low-voltage embedded flash （eFlash） memory applications. The topology of the sense amplifier is based on current mode comparison. Moreover, an offset-voltage elimination technique is employed to improve the sensing performance under a small memory cell current. The proposed sense amplifier is designed based on a GSMC 130 nm eFlash process, and the sense time is 0.43 ns at 1.5 V, corresponding to a 46% improvement over the conventional technologies.