Synthesis of Nonlinear Control of Switching Topologies of Buck-Boost Converter Using Fuzzy Logic on Field Programmable Gate Array (FPGA)

An intelligent fuzzy logic inference pipeline for the control of a dc-dc buck-boost converter was designed and built using a semi-custom VLSI chip. The fuzzy linguistics describing the switching topologies of the converter was mapped into a look-up table that was synthesized into a set of Boolean equations. A VLSI chip–a field programmable gate array (FPGA) was used to implement the Boolean equations. Features include the size of RAM chip independent of number of rules in the knowledge base, on-chip fuzzification and defuzzification, faster response with speeds over giga fuzzy logic inferences per sec (FLIPS), and an inexpensive VLSI chip. The key application areas are: 1) on-chip integrated controllers;and 2) on-chip co-integration for entire system of sensors, circuits, controllers, and detectors for building complete instrument systems.

A New Design Method for Variable Digital Filter Based on Field Programmable Gate Array(FPGA)

In order to obtain variable characteristics,the digital filter's type,number of taps and coefficients should be changed constantly such that the desired frequency-domain characteristics can be obtained.This paper proposes a method for self-programmable variable digital filter(VDF) design based on field programmable gate array(FPGA).We implement a digital filter system by using custom embedded micro-processor,programmable finite impulse response(P-FIR) macro module,coefficient-loader,clock manager and analog/digital(A/D) or digital/analog(D/A) controller and other modules.The self-programmable VDF can provide the best solution for realization of digital filter algorithms,which are the low-pass,high-pass,band-pass and band-stop filter algorithms with variable frequency domain characteristics.The design examples with minimum 1 to maximum 32 taps FIR filter,based on Modelsim post-routed simulation and onboard running on XUPV5-LX110T,are provided to demonstrate the effectiveness of the proposed method.

Fault Prediction and Diagnosis of Warship Equipment Field Programmable Gate Array Software

In order to solve the current high failure rate of warship equipment field programmable gate array( FPGA) software,fault detection is not timely enough and FPGA detection equipment is expensive and so on. After in-depth research,this paper proposes a warship equipment FPGA software based on Xilinx integrated development environment( ISE) and ModelSim software.Functional simulation and timing simulation to verify the correctness of the logic design of the FPGA,this method is very convenient to view the signal waveform inside the FPGA program to help FPGA test engineers to achieve FPGA fault prediction and diagnosis. This test method has important engineering significance for the upgrading of warship equipment.

MIXED-GRAINED CMOS FIELD PROGRAMMABLE ANALOG ARRAY FOR SMART SENSORY APPLICATIONS

The drive towards shorter design cycles for analog integrated circuits has given impetus to the development of Field Programmable Analog Arrays(FPAAs),which are the analogue counterparts of Field Programmable Gate Arrays(FPGAs).In this paper,we present a new design methodology which using FPAA as a powerful analog front-end processing platform in the smart sensory microsystem.The proposed FPAA contains 16 homogeneous mixed-grained Configurable Analog Blocks(CABs) which house a variety of processing elements especially the proposed fine-grained Core Configurable Amplifiers(CCAs).The high flexible CABs allow the FPAA operating in both continuous-time and discrete-time approaches suitable to support variety of sensors.To reduce the nonideal parasitic effects and save area,the fat-tree interconnection network is adopted in this FPAA.The functionality of this FPAA is demonstrated through embedding of voltage and capacitive sensor signal readout circuits and a configurable band pass filter.The minimal detectable voltage and capacitor achieves 38 uV and 8.3 aF respectively within 100 Hz sensor bandwidth.The power consumption comparison of CCA in three applications shows that the FPAA has high power efficiency.And the simulation results also show that the FPAA has good tolerance with wide PVT variations.

FPGA implementation of bit-stream neuron and perceptron based on sigma delta modulation

To solve the excessive huge scale problem of the traditional multi-bit digital artificial neural network（ANN） hardware implementation methods,a bit-stream ANN hardware implementation method based on sigma delta（ΣΔ） modulation is presented.The bit-stream adder,multiplier,threshold function unit and fully digital ΣΔ modulator are implemented in a field programmable gate array（FPGA）,and these bit-stream arithmetical units are employed to build the bit-stream artificial neuron.The function of the bit-stream artificial neuron is verified through the realization of the logic function and a linear classifier.The bit-stream perceptron based on the bit-stream artificial neuron with the pre-processed structure is proved to have the ability of nonlinear classification.The FPGA resource utilization of the bit-stream artificial neuron shows that the bit-stream ANN hardware implementation method can significantly reduce the demand of the ANN hardware resources.

Mosaic line-scan camera based on FPGA

Because single line-scan camera loses light in the edge of the sensor when the field of view is large, a mosaic cam- era based on field programmable gate array （FPGA） is presented by putting multiple cameras arranged in a straight line to share the field of view and reduce the view angle of every camera. For detecting doping micro particles with the designed mosaic line-scan camera, a detection algorithm of the target＇s location in FPGA is proposed. Finally, the practicability and stability of the system were validated experimentally. The results of the experiment show that the camera can get images clearly with less light loss and can accurately distinguish the target and the background.

Design of IRIG-B(AC) encoder based on FPGA

InterRange Instrumentation Group（IRIG-B（AC））code is usually used in the shooting range test for time information transmission and systems time synchronization.According to IRIG-B（AC）code format and modulation principle,this paper presents IRIG-B（AC）coding circuit design scheme based on field programmable gate array（FPGA）.The B（AC）code signal is generated by AD7245,a digital-to-analog（D/A）converter.After amplified,the signal can be used directly for system time synchronization,and the amplitude of the signal can be adjusted according to different requirements.The IRIG-B（AC）encoder designed has been verified by test.The test results show that it can output accurate time information and has higher practicality.

FPGA-Based Efficient Programmable Polyphase FIR Filter

The modelling, design and implementation of a high-speed programmable polyphase finite impulse response (FIR) filter with field programmable gate array (FPGA) technology are described. This FIR filter can run automatically according to the programmable configuration word including symmetry/asymmetry, odd/even taps, from 32 taps up to 256 taps. The filter with 12 bit signal and 12 bit coefficient word-length has been realized on a Xilinx VirtexⅡ-v1500 device and operates at the maximum sampling frequency of (160 MHz.)

A multi-directional controllable multi-scroll conservative chaos generator:Modelling,analysis,and FPGA implementation

Combing with the generalized Hamiltonian system theory,by introducing a special form of sinusoidal function,a class of n-dimensional(n=1,2,3)controllable multi-scroll conservative chaos with complicated dynamics is constructed.The dynamics characteristics including bifurcation behavior and coexistence of the system are analyzed in detail,the latter reveals abundant coexisting flows.Furthermore,the proposed system passes the NIST tests and has been implemented physically by FPGA.Compared to the multi-scroll dissipative chaos,the experimental portraits of the proposed system show better ergodicity,which have potential application value in secure communication and image encryption.

Implementation of a kind of FPGA-based binary phase coded radar signal processor architecture

A flexible field programmable gate array based radar signal processor is presented. The radar signal processor mainly consists of five functional modules： radar system timer, binary phase coded pulse compression（PC）, moving target detection （MTD）, constant false alarm rate （CFAR） and target dots processing. Preliminary target dots information is obtained in PC, MTD, and CFAR modules and Nios I! CPU is used for target dots combination and false sidelobe target removing. Sys- tem on programmable chip （SOPC） technique is adopted in the system in which SDRAM is used to cache data. Finally, a FPGA-based binary phase coded radar signal processor is realized and simula- tion result is given.

TIMING SLACK OPTIMIZATION APPROACH USING FPGA HYBRID ROUTING STRATEGY OF RIP-UP-RETRY AND PATHFINDER

To improve the path slack of Field Programmable Gate Array(FPGA), this paper proposes a timing slack optimization approach which utilizes the hybrid routing strategy of rip-up-retry and pathfinder. Firstly, effect of process variations on path slack is analyzed, and by constructing a collocation table of delay model that takes into account the multi-corner process, the complex statistical static timing analysis is successfully translated into a simple classical static timing analysis. Then, based on the hybrid routing strategy of rip-up-retry and pathfinder, by adjusting the critical path which detours a long distance, the critical path delay is reduced and the path slack is optimized. Experimental results show that, using the hybrid routing strategy, the number of paths with negative slack can be optimized(reduced) by 85.8% on average compared with the Versatile Place and Route(VPR) timing-driven routing algorithm, while the run-time is only increased by 15.02% on average.

FPGA-Based Traffic Sign Recognition for Advanced Driver Assistance Systems

This paper presents the implementation of an embedded automotive system that detects and recognizes traffic signs within a video stream. In addition, it discusses the recent advances in driver assistance technologies and highlights the safety motivations for smart in-car embedded systems. An algorithm is presented that processes RGB image data, extracts relevant pixels, filters the image, labels prospective traffic signs and evaluates them against template traffic sign images. A reconfigurable hardware system is described which uses the Virtex-5 Xilinx FPGA and hardware/software co-design tools in order to create an embedded processor and the necessary hardware IP peripherals. The implementation is shown to have robust performance results, both in terms of timing and accuracy.

Incremental Min-Period Retiming Algorithm for FPGA Synthesis Based on Influence of Fan-Outs

An improved linear-time retiming algorithm is proposed to incrementally optimize the clock period, espe cially considering the influence of the in-out degree of the critical combinational elements. Firslly, the critical elements are selected from all the critical combinational elements to retime. Secondly, for the nodes that cannot be performed with such retiming, register sharing is implemented while the path delay is kept unchanged. The incremental algorithm can be applied with the technology mapping to minimize the critical path delay and obtain fewer registers in the re- timed circuit with the near-optimal clock period. Compared with Singh＇s incremental algorithm, experiments show that the proposed algorithm can reduce the flip-flop count by 11% and look-up table （LUT） count by 5% while improv- ing the minimum clock period by 6%. The runtime is also reduced by 9% of the design flow.

Fast Rail Defect Inspection Based on Half-Cycle Power Demodulation Method and FPGA Implementation

In this paper,a fast-speed and real-time online rail inspection method based on half-cycle orthogonal power demodulation algorithm is proposed.For this method,the power characters of de-tection signal which represent the degree of rail track can be calculated using only half-cycle detec-tion signal because of the symmetry characteristic of detected sine signal and reference signal.The theoretical analysis,simulation results and experiment results show that the demodulation preci-sion of proposed method is almost equal to fast Fourier transform(FFT)demodulation method and orthogonal demodulation method,but has high demodulation efficiency and less FPGA resources cost.A high-speed experiment system based on three coils structured sensor is built for rail inspec-tion experiment at a moving speed of 200 km/h.The experiment results show that proposed meth-od is more effective for rail inspection and the time resolution of proposed method is double of clas-sic method that based on FFT and orthogonal.

Low complexity SEU mitigation technique for SRAM-based FPGAs

An internal single event upset（SEU）mitigation technique is proposed,which reads back the configuration frames from the static random access memory（SRAM）-based field programmable gate array（FPGA）through an internal port and compares them with those stored in the radiationhardened memory to detect and correct SEUs.Triple modular redundancy（TMR）,which triplicates the circuit of the technique and uses majority voters to isolate any single upset within it,is used to enhance the reliability.Performance analysis shows that the proposed technique can satisfy the requirement of ordinary aerospace missions with less power dissipation,size and weight.The fault injection experiment validates that the proposed technique is capable of correcting most errors to protect spaceborne facilities from SEUs.

RESEARCH ON THE PACKING ALGORITHM FOR ANTI-SEU OF FPGA BASED ON TRIPLE MODULAR REDUNDANCY AND THE NUMBERS OF FAN-OUTS OF THE NET

Static Random Access Memory(SRAM) based Field Programmable Gate Array(FPGA) is widely applied in the field of aerospace, whose anti-SEU(Single Event Upset) capability becomes more and more important. To improve anti-FPGA SEU capability, the registers of the circuit netlist are tripled and divided into three categories in this study. By the packing algorithm, the registers of triple modular redundancy are loaded into different configurable logic block. At the same time, the packing algorithm considers the effect of large fan-out nets. The experimental results show that the algorithm successfully realize the packing of the register of Triple Modular Redundancy(TMR). Comparing with Timing Versatile PACKing(TVPACK), the algorithm in this study is able to obtain a 11% reduction of the number of the nets in critical path, and a 12% reduction of the time delay in critical path on average when TMR is not considered. Especially, some critical path delay of circuit can be improved about 33%.

Implementing kinematics computation in FPGA co-processor for a 6-DOF space manipulator

Based on the coordinate rotation digital computer(CORDIC)algorithm,the high-speed kinematicscalculation for a six degree of freedom(DOF)space manipulator is implemented in a field programmablegate array(FPGA)co-processor.A pipeline architecture is adopted to reduce the complexity and time-consumption of the kinematics calculation .The CORDIC soft-core and the CORDIC-based pipelined kine-matics calculation co-processor are described with the very-high-speed integrated circuit hardware descrip-tion language(VHDL)language and realized in the FPGA .Finally,the feasibility of the design is vali-dated in the Spartan-3 FPGA of Xilinx Inc.,and the performance specifications of FPGA co-processor arediscussed.The results show that time-consumption of the kinematics calculation is greatly reduced.

Investigational Validation of PV Based DCD-MLI Using Simplified SVM Algorithm Utilizing FPGA Tied with Independent Sources

This paper presents the independent source tied photovoltaic (PV) based three-phase three-level diode-clamped-multilevel inverter (DCD-MLI) utilizing field programmable gate array (FPGA) controller. The maximum power point (MPP) is tracked by using fuzzy logic algorithm. Employed for gating signal generation, the space vector modulation (SVM) strategy eradicates the complexity in determining the reference vector location, the ON-time calculations and switching state selection. A digital proportional integral (PI) control algorithm is implemented on a FPGA to keep the current injected into the independent source (grid) sinusoidal and to achieve high dynamic performance with low total harmonic distortion (THD) of output voltage and output current which are 0.97% and 1.26%. With the proposed configuration, the adjustments of modulation index and phase angle are synthesized onto a FPGA by means of hardware description language (VHDL). The efficacy of the scheme is verified through simulation study. To confirm the feasibility of the scheme, experimental studies are carried out on a scaled-down laboratory prototype.

Machine learning algorithm partially reconfigured on FPGA for an image edge detection system

Unmanned aerial vehicles(UAVs)have been widely used in military,medical,wireless communications,aerial surveillance,etc.One key topic involving UAVs is pose estimation in autonomous navigation.A standard procedure for this process is to combine inertial navigation system sensor information with the global navigation satellite system(GNSS)signal.However,some factors can interfere with the GNSS signal,such as ionospheric scintillation,jamming,or spoofing.One alternative method to avoid using the GNSS signal is to apply an image processing approach by matching UAV images with georeferenced images.But a high effort is required for image edge extraction.Here a support vector regression(SVR)model is proposed to reduce this computational load and processing time.The dynamic partial reconfiguration(DPR)of part of the SVR datapath is implemented to accelerate the process,reduce the area,and analyze its granularity by increasing the grain size of the reconfigurable region.Results show that the implementation in hardware is 68 times faster than that in software.This architecture with DPR also facilitates the low power consumption of 4 mW,leading to a reduction of 57%than that without DPR.This is also the lowest power consumption in current machine learning hardware implementations.Besides,the circuitry area is 41 times smaller.SVR with Gaussian kernel shows a success rate of 99.18%and minimum square error of 0.0146 for testing with the planning trajectory.This system is useful for adaptive applications where the user/designer can modify/reconfigure the hardware layout during its application,thus contributing to lower power consumption,smaller hardware area,and shorter execution time.

GJB 5000B在FPGA工程中的应用分析

为引入软件工程化管理办法对设计开发实践实施管理,结合GJB 5000B体系要求,对现场可编程逻辑门阵列(Field Programmable Gate Array,FPGA)的设计开发流程和GJB 5000B的工程实践要求进行梳理、比对和分析,并提出一套FPGA开发管理在GJB 5000B推进实践中的实施办法。研究成果可为GJB 5000B在FPGA工程中的应用提供一定参考。