Unmanned aerial vehicles(UAVs)have been widely used in military,medical,wireless communications,aerial surveillance,etc.One key topic involving UAVs is pose estimation in autonomous navigation.A standard procedure for...Unmanned aerial vehicles(UAVs)have been widely used in military,medical,wireless communications,aerial surveillance,etc.One key topic involving UAVs is pose estimation in autonomous navigation.A standard procedure for this process is to combine inertial navigation system sensor information with the global navigation satellite system(GNSS)signal.However,some factors can interfere with the GNSS signal,such as ionospheric scintillation,jamming,or spoofing.One alternative method to avoid using the GNSS signal is to apply an image processing approach by matching UAV images with georeferenced images.But a high effort is required for image edge extraction.Here a support vector regression(SVR)model is proposed to reduce this computational load and processing time.The dynamic partial reconfiguration(DPR)of part of the SVR datapath is implemented to accelerate the process,reduce the area,and analyze its granularity by increasing the grain size of the reconfigurable region.Results show that the implementation in hardware is 68 times faster than that in software.This architecture with DPR also facilitates the low power consumption of 4 mW,leading to a reduction of 57%than that without DPR.This is also the lowest power consumption in current machine learning hardware implementations.Besides,the circuitry area is 41 times smaller.SVR with Gaussian kernel shows a success rate of 99.18%and minimum square error of 0.0146 for testing with the planning trajectory.This system is useful for adaptive applications where the user/designer can modify/reconfigure the hardware layout during its application,thus contributing to lower power consumption,smaller hardware area,and shorter execution time.展开更多
In order to obtain variable characteristics,the digital filter's type,number of taps and coefficients should be changed constantly such that the desired frequency-domain characteristics can be obtained.This paper ...In order to obtain variable characteristics,the digital filter's type,number of taps and coefficients should be changed constantly such that the desired frequency-domain characteristics can be obtained.This paper proposes a method for self-programmable variable digital filter(VDF) design based on field programmable gate array(FPGA).We implement a digital filter system by using custom embedded micro-processor,programmable finite impulse response(P-FIR) macro module,coefficient-loader,clock manager and analog/digital(A/D) or digital/analog(D/A) controller and other modules.The self-programmable VDF can provide the best solution for realization of digital filter algorithms,which are the low-pass,high-pass,band-pass and band-stop filter algorithms with variable frequency domain characteristics.The design examples with minimum 1 to maximum 32 taps FIR filter,based on Modelsim post-routed simulation and onboard running on XUPV5-LX110T,are provided to demonstrate the effectiveness of the proposed method.展开更多
As a core component in intelligent edge computing,deep neural networks(DNNs)will increasingly play a critically important role in addressing the intelligence-related issues in the industry domain,like smart factories ...As a core component in intelligent edge computing,deep neural networks(DNNs)will increasingly play a critically important role in addressing the intelligence-related issues in the industry domain,like smart factories and autonomous driving.Due to the requirement for a large amount of storage space and computing resources,DNNs are unfavorable for resource-constrained edge computing devices,especially for mobile terminals with scarce energy supply.Binarization of DNN has become a promising technology to achieve a high performance with low resource consumption in edge computing.Field-programmable gate array(FPGA)-based acceleration can further improve the computation efficiency to several times higher compared with the central processing unit(CPU)and graphics processing unit(GPU).This paper gives a brief overview of binary neural networks(BNNs)and the corresponding hardware accelerator designs on edge computing environments,and analyzes some significant studies in detail.The performances of some methods are evaluated through the experiment results,and the latest binarization technologies and hardware acceleration methods are tracked.We first give the background of designing BNNs and present the typical types of BNNs.The FPGA implementation technologies of BNNs are then reviewed.Detailed comparison with experimental evaluation on typical BNNs and their FPGA implementation is further conducted.Finally,certain interesting directions are also illustrated as future work.展开更多
This paper proposes a parallel cyclic shift structure of address decoder to realize a high-throughput encoding and decoding method for irregular-quasi-cyclic low-density parity-check(IR-QC-LDPC)codes,with a dual-diago...This paper proposes a parallel cyclic shift structure of address decoder to realize a high-throughput encoding and decoding method for irregular-quasi-cyclic low-density parity-check(IR-QC-LDPC)codes,with a dual-diagonal parity structure.A normalized min-sum algorithm(NMSA)is employed for decoding.The whole verification of the encoding and decoding algorithm is simulated with Matlab,and the code rates of 5/6 and 2/3 are selected respectively for the initial bit error ratio as 6%and 1.04%.Based on the results of simulation,multi-code rates are compatible with different basis matrices.Then the simulated algorithms of encoder and decoder are migrated and implemented on the field programmable gate array(FPGA).The 183.36 Mbps throughput of encoder and the average 27.85 Mbps decoding throughput with the initial bit error ratio 6%are realized based on FPGA.展开更多
Field Programmable Gate Array(FPGA) is an efficient reconfigurable integrated circuit platform and has become a core signal processing microchip device of digital systems over the last decade. With the rapid developme...Field Programmable Gate Array(FPGA) is an efficient reconfigurable integrated circuit platform and has become a core signal processing microchip device of digital systems over the last decade. With the rapid development of semiconductor technology, the performance and system integration of FPGA devices have been significantly progressed, and at the same time new challenges arise. The design of FPGA architecture is required to evolve to meet these challenges, while also taking advantage of ever increased microchip density. This survey reviews the recent development of advanced FPGA architectures, including improvement of the programming technologies, logic blocks, interconnects, and embedded resources. Moreover, some important emerging design issues of FPGA architectures, such as novel memory based FPGAs and 3D FPGAs, are also presented to provide an outlook for future FPGA development.展开更多
As a coprocessor, field-programmable gate array (FPGA) is the hardware computing processor accelerating the computing capacity of coraputers. To efficiently manage the hardware free resources for the placing of task...As a coprocessor, field-programmable gate array (FPGA) is the hardware computing processor accelerating the computing capacity of coraputers. To efficiently manage the hardware free resources for the placing of tasks on FPGA and take full advantage of the partially reconfigurable units, good utilization of chip resources is an important and necessary work. In this paper, a new method is proposed to find the complete set of maximal free resource rectangles based on the cross point of edge lines of running tasks on FPGA area, and the prove process is provided to make sure the correctness of this method.展开更多
The modelling, design and implementation of a high-speed programmable polyphase finite impulse response (FIR) filter with field programmable gate array (FPGA) technology are described. This FIR filter can run automati...The modelling, design and implementation of a high-speed programmable polyphase finite impulse response (FIR) filter with field programmable gate array (FPGA) technology are described. This FIR filter can run automatically according to the programmable configuration word including symmetry/asymmetry, odd/even taps, from 32 taps up to 256 taps. The filter with 12 bit signal and 12 bit coefficient word-length has been realized on a Xilinx VirtexⅡ-v1500 device and operates at the maximum sampling frequency of (160 MHz.)展开更多
Afuzzy controller based oni mproved Generalized-Membership-Function(GMF) algorithmfor afuel cell generationsys-tem wasintroduced.Under the demands on control in application of the converter,a Field Programmable Gate A...Afuzzy controller based oni mproved Generalized-Membership-Function(GMF) algorithmfor afuel cell generationsys-tem wasintroduced.Under the demands on control in application of the converter,a Field Programmable Gate Array(FPGA) re-alization method to manage the power flow was given.This control systembased onthe proposed modified GMF was proved to bea universal approxi mation systemin theory.The fuzzy control technique was combined with Eletronic Design Automatic(EDA)technique and a paralleling fuzzy controller was i mplemented in FPGA.Paralleling fuzzy controller based oni mproved GMF algo-rithm wasi mplemented on a Cyclone FPGA.The result of si mulation based on QuartusII confirmed the validity of the proposed method.展开更多
Combing with the generalized Hamiltonian system theory,by introducing a special form of sinusoidal function,a class of n-dimensional(n=1,2,3)controllable multi-scroll conservative chaos with complicated dynamics is co...Combing with the generalized Hamiltonian system theory,by introducing a special form of sinusoidal function,a class of n-dimensional(n=1,2,3)controllable multi-scroll conservative chaos with complicated dynamics is constructed.The dynamics characteristics including bifurcation behavior and coexistence of the system are analyzed in detail,the latter reveals abundant coexisting flows.Furthermore,the proposed system passes the NIST tests and has been implemented physically by FPGA.Compared to the multi-scroll dissipative chaos,the experimental portraits of the proposed system show better ergodicity,which have potential application value in secure communication and image encryption.展开更多
To improve the path slack of Field Programmable Gate Array(FPGA), this paper proposes a timing slack optimization approach which utilizes the hybrid routing strategy of rip-up-retry and pathfinder. Firstly, effect of ...To improve the path slack of Field Programmable Gate Array(FPGA), this paper proposes a timing slack optimization approach which utilizes the hybrid routing strategy of rip-up-retry and pathfinder. Firstly, effect of process variations on path slack is analyzed, and by constructing a collocation table of delay model that takes into account the multi-corner process, the complex statistical static timing analysis is successfully translated into a simple classical static timing analysis. Then, based on the hybrid routing strategy of rip-up-retry and pathfinder, by adjusting the critical path which detours a long distance, the critical path delay is reduced and the path slack is optimized. Experimental results show that, using the hybrid routing strategy, the number of paths with negative slack can be optimized(reduced) by 85.8% on average compared with the Versatile Place and Route(VPR) timing-driven routing algorithm, while the run-time is only increased by 15.02% on average.展开更多
This paper introduces a switched hyperchaotic system that changes its behavior randomly from one subsystem to another via two switch functions, and its characteristics of symmetry, dissipation, equilibrium, bifurcatio...This paper introduces a switched hyperchaotic system that changes its behavior randomly from one subsystem to another via two switch functions, and its characteristics of symmetry, dissipation, equilibrium, bifurcation diagram, basic dynamics have been analyzed. The hardware implementation of the system is based on Field Programmable Gate Array (FPGA). It is shown that the experimental results are identical with numerical simulations, and the chaotic trajectories are much more complex.展开更多
A flexible field programmable gate array based radar signal processor is presented. The radar signal processor mainly consists of five functional modules: radar system timer, binary phase coded pulse compression(PC...A flexible field programmable gate array based radar signal processor is presented. The radar signal processor mainly consists of five functional modules: radar system timer, binary phase coded pulse compression(PC), moving target detection (MTD), constant false alarm rate (CFAR) and target dots processing. Preliminary target dots information is obtained in PC, MTD, and CFAR modules and Nios I! CPU is used for target dots combination and false sidelobe target removing. Sys- tem on programmable chip (SOPC) technique is adopted in the system in which SDRAM is used to cache data. Finally, a FPGA-based binary phase coded radar signal processor is realized and simula- tion result is given.展开更多
基金financially supported by the National Council for Scientific and Technological Development(CNPq,Brazil),Swedish-Brazilian Research and Innovation Centre(CISB),and Saab AB under Grant No.CNPq:200053/2022-1the National Council for Scientific and Technological Development(CNPq,Brazil)under Grants No.CNPq:312924/2017-8 and No.CNPq:314660/2020-8.
文摘Unmanned aerial vehicles(UAVs)have been widely used in military,medical,wireless communications,aerial surveillance,etc.One key topic involving UAVs is pose estimation in autonomous navigation.A standard procedure for this process is to combine inertial navigation system sensor information with the global navigation satellite system(GNSS)signal.However,some factors can interfere with the GNSS signal,such as ionospheric scintillation,jamming,or spoofing.One alternative method to avoid using the GNSS signal is to apply an image processing approach by matching UAV images with georeferenced images.But a high effort is required for image edge extraction.Here a support vector regression(SVR)model is proposed to reduce this computational load and processing time.The dynamic partial reconfiguration(DPR)of part of the SVR datapath is implemented to accelerate the process,reduce the area,and analyze its granularity by increasing the grain size of the reconfigurable region.Results show that the implementation in hardware is 68 times faster than that in software.This architecture with DPR also facilitates the low power consumption of 4 mW,leading to a reduction of 57%than that without DPR.This is also the lowest power consumption in current machine learning hardware implementations.Besides,the circuitry area is 41 times smaller.SVR with Gaussian kernel shows a success rate of 99.18%and minimum square error of 0.0146 for testing with the planning trajectory.This system is useful for adaptive applications where the user/designer can modify/reconfigure the hardware layout during its application,thus contributing to lower power consumption,smaller hardware area,and shorter execution time.
基金Science &Technology Plan Foundation of Hunan Province,China(No.2010F3102)Science Research Foundation of Hunan Province,China(No.08C392)
文摘In order to obtain variable characteristics,the digital filter's type,number of taps and coefficients should be changed constantly such that the desired frequency-domain characteristics can be obtained.This paper proposes a method for self-programmable variable digital filter(VDF) design based on field programmable gate array(FPGA).We implement a digital filter system by using custom embedded micro-processor,programmable finite impulse response(P-FIR) macro module,coefficient-loader,clock manager and analog/digital(A/D) or digital/analog(D/A) controller and other modules.The self-programmable VDF can provide the best solution for realization of digital filter algorithms,which are the low-pass,high-pass,band-pass and band-stop filter algorithms with variable frequency domain characteristics.The design examples with minimum 1 to maximum 32 taps FIR filter,based on Modelsim post-routed simulation and onboard running on XUPV5-LX110T,are provided to demonstrate the effectiveness of the proposed method.
基金supported by the Natural Science Foundation of Sichuan Province of China under Grant No.2022NSFSC0500the National Natural Science Foundation of China under Grant No.62072076.
文摘As a core component in intelligent edge computing,deep neural networks(DNNs)will increasingly play a critically important role in addressing the intelligence-related issues in the industry domain,like smart factories and autonomous driving.Due to the requirement for a large amount of storage space and computing resources,DNNs are unfavorable for resource-constrained edge computing devices,especially for mobile terminals with scarce energy supply.Binarization of DNN has become a promising technology to achieve a high performance with low resource consumption in edge computing.Field-programmable gate array(FPGA)-based acceleration can further improve the computation efficiency to several times higher compared with the central processing unit(CPU)and graphics processing unit(GPU).This paper gives a brief overview of binary neural networks(BNNs)and the corresponding hardware accelerator designs on edge computing environments,and analyzes some significant studies in detail.The performances of some methods are evaluated through the experiment results,and the latest binarization technologies and hardware acceleration methods are tracked.We first give the background of designing BNNs and present the typical types of BNNs.The FPGA implementation technologies of BNNs are then reviewed.Detailed comparison with experimental evaluation on typical BNNs and their FPGA implementation is further conducted.Finally,certain interesting directions are also illustrated as future work.
基金supported by the National Natural Science Foundation of China(11705191)the Anhui Provincial Natural Science Foundation(1808085QF180)the Natural Science Foundation of Shanghai(18ZR1443600)
文摘This paper proposes a parallel cyclic shift structure of address decoder to realize a high-throughput encoding and decoding method for irregular-quasi-cyclic low-density parity-check(IR-QC-LDPC)codes,with a dual-diagonal parity structure.A normalized min-sum algorithm(NMSA)is employed for decoding.The whole verification of the encoding and decoding algorithm is simulated with Matlab,and the code rates of 5/6 and 2/3 are selected respectively for the initial bit error ratio as 6%and 1.04%.Based on the results of simulation,multi-code rates are compatible with different basis matrices.Then the simulated algorithms of encoder and decoder are migrated and implemented on the field programmable gate array(FPGA).The 183.36 Mbps throughput of encoder and the average 27.85 Mbps decoding throughput with the initial bit error ratio 6%are realized based on FPGA.
基金Supported by National Natural Science Foundation of China(No.61271149)National High Technology Research and Development Program of China(No.2012AA-012301)National Science and Technology Major Project of China(No.2013ZX03006004)
文摘Field Programmable Gate Array(FPGA) is an efficient reconfigurable integrated circuit platform and has become a core signal processing microchip device of digital systems over the last decade. With the rapid development of semiconductor technology, the performance and system integration of FPGA devices have been significantly progressed, and at the same time new challenges arise. The design of FPGA architecture is required to evolve to meet these challenges, while also taking advantage of ever increased microchip density. This survey reviews the recent development of advanced FPGA architectures, including improvement of the programming technologies, logic blocks, interconnects, and embedded resources. Moreover, some important emerging design issues of FPGA architectures, such as novel memory based FPGAs and 3D FPGAs, are also presented to provide an outlook for future FPGA development.
基金Project supported by the Shanghai Leading Academic Discipline Project(Grant No.J50103)the Natural Science Foundation of Jiangxi Province(Grant No.2010GZS0031)the Science Technology Project of Jiangxi Province(Grant No.2010BGB00604)
文摘As a coprocessor, field-programmable gate array (FPGA) is the hardware computing processor accelerating the computing capacity of coraputers. To efficiently manage the hardware free resources for the placing of tasks on FPGA and take full advantage of the partially reconfigurable units, good utilization of chip resources is an important and necessary work. In this paper, a new method is proposed to find the complete set of maximal free resource rectangles based on the cross point of edge lines of running tasks on FPGA area, and the prove process is provided to make sure the correctness of this method.
文摘The modelling, design and implementation of a high-speed programmable polyphase finite impulse response (FIR) filter with field programmable gate array (FPGA) technology are described. This FIR filter can run automatically according to the programmable configuration word including symmetry/asymmetry, odd/even taps, from 32 taps up to 256 taps. The filter with 12 bit signal and 12 bit coefficient word-length has been realized on a Xilinx VirtexⅡ-v1500 device and operates at the maximum sampling frequency of (160 MHz.)
文摘Afuzzy controller based oni mproved Generalized-Membership-Function(GMF) algorithmfor afuel cell generationsys-tem wasintroduced.Under the demands on control in application of the converter,a Field Programmable Gate Array(FPGA) re-alization method to manage the power flow was given.This control systembased onthe proposed modified GMF was proved to bea universal approxi mation systemin theory.The fuzzy control technique was combined with Eletronic Design Automatic(EDA)technique and a paralleling fuzzy controller was i mplemented in FPGA.Paralleling fuzzy controller based oni mproved GMF algo-rithm wasi mplemented on a Cyclone FPGA.The result of si mulation based on QuartusII confirmed the validity of the proposed method.
基金Project supported by the Natural Science Foundation of Tianjin,China(Grant No.18JCYBJC87700)the Natural Science Foundation of China(Grant No.61603274)。
文摘Combing with the generalized Hamiltonian system theory,by introducing a special form of sinusoidal function,a class of n-dimensional(n=1,2,3)controllable multi-scroll conservative chaos with complicated dynamics is constructed.The dynamics characteristics including bifurcation behavior and coexistence of the system are analyzed in detail,the latter reveals abundant coexisting flows.Furthermore,the proposed system passes the NIST tests and has been implemented physically by FPGA.Compared to the multi-scroll dissipative chaos,the experimental portraits of the proposed system show better ergodicity,which have potential application value in secure communication and image encryption.
基金Supported by National High Technology Research and Develop Program of China(No.2012AA012301)the CAS/SAFEA International Partnership Program for Creative Research Teams
文摘To improve the path slack of Field Programmable Gate Array(FPGA), this paper proposes a timing slack optimization approach which utilizes the hybrid routing strategy of rip-up-retry and pathfinder. Firstly, effect of process variations on path slack is analyzed, and by constructing a collocation table of delay model that takes into account the multi-corner process, the complex statistical static timing analysis is successfully translated into a simple classical static timing analysis. Then, based on the hybrid routing strategy of rip-up-retry and pathfinder, by adjusting the critical path which detours a long distance, the critical path delay is reduced and the path slack is optimized. Experimental results show that, using the hybrid routing strategy, the number of paths with negative slack can be optimized(reduced) by 85.8% on average compared with the Versatile Place and Route(VPR) timing-driven routing algorithm, while the run-time is only increased by 15.02% on average.
文摘This paper introduces a switched hyperchaotic system that changes its behavior randomly from one subsystem to another via two switch functions, and its characteristics of symmetry, dissipation, equilibrium, bifurcation diagram, basic dynamics have been analyzed. The hardware implementation of the system is based on Field Programmable Gate Array (FPGA). It is shown that the experimental results are identical with numerical simulations, and the chaotic trajectories are much more complex.
基金Supported by the Ministerial Level Advanced Research Foundation (SP240012)
文摘A flexible field programmable gate array based radar signal processor is presented. The radar signal processor mainly consists of five functional modules: radar system timer, binary phase coded pulse compression(PC), moving target detection (MTD), constant false alarm rate (CFAR) and target dots processing. Preliminary target dots information is obtained in PC, MTD, and CFAR modules and Nios I! CPU is used for target dots combination and false sidelobe target removing. Sys- tem on programmable chip (SOPC) technique is adopted in the system in which SDRAM is used to cache data. Finally, a FPGA-based binary phase coded radar signal processor is realized and simula- tion result is given.