A new hybrid FPGA architecture is proposed. The logic tile,which consists of a logic cluster and related connection boxes （CBs）, can be configured as either programmable logic arrays （PLAs） or look-up tables （LUT...A new hybrid FPGA architecture is proposed. The logic tile,which consists of a logic cluster and related connection boxes （CBs）, can be configured as either programmable logic arrays （PLAs） or look-up tables （LUTs）, This architecture can be classified as an AND-LUT array. PLAs are suitable for the implementation of high fan-in logic circuits, while LUTs are used to implement low fan-in logic circuits. As a result, the proposed hybrid FPGA architecture （HFA） is more flexible to improve logic density. Experiments based on MCNC benchmark circuits were performed in both the hybrid architecture and conventional LUT-based symmetrical FPGA architecture in term of area consumption. Preliminary results indicate that on average, the area is reduced by 46% using the new hybrid architecture.展开更多
为开发高度集成的五指机器人灵巧手,提出了采用DSP(Digital Signal Processor)+FPGA(Field Programmable Gate Array)控制结构的模块化嵌入式手指控制系统设计方法。实现了采用单电流传感器检测全桥控制下相电流及相电流过流双保护。为...为开发高度集成的五指机器人灵巧手,提出了采用DSP(Digital Signal Processor)+FPGA(Field Programmable Gate Array)控制结构的模块化嵌入式手指控制系统设计方法。实现了采用单电流传感器检测全桥控制下相电流及相电流过流双保护。为解决手指DSP和FPGA之间如何稳定、高效通信的难题,结合先进先出FIFO(First In First Out)寄存器,设计了基于串行通信接口SCI(Serial Communications Interface)和RS485总线的多中断差分通信系统。实验证明,这种DSP+FPGA控制结构及模块化的设计,使得手指控制部分得以高度集成,同时DLR/HITII灵巧手获得很好的整体性能和稳定性。展开更多
We develop a 3D bounded slice-surface grid （3D-BSSG） structure for representation and introduce the solution space smoothing technique to search for the optimal solution. Experiment results demonstrate that a 3D-BSS...We develop a 3D bounded slice-surface grid （3D-BSSG） structure for representation and introduce the solution space smoothing technique to search for the optimal solution. Experiment results demonstrate that a 3D-BSSG structure based algorithm is very effective and efficient.展开更多
The architecture of a BioAccel (internal code) chip for RNA secondary structure prediction is described in the letter. The system is based on a BioBus (internal code), whose distinguishing features are: Two separated ...The architecture of a BioAccel (internal code) chip for RNA secondary structure prediction is described in the letter. The system is based on a BioBus (internal code), whose distinguishing features are: Two separated control and data channels, and a slave-associated arbitration scheme. Two reference systems based on the AMBA AHB bus and Coreconnect bus are introduced to evaluate the performance of the system. The simulation results are attractive. The average communication bandwidth of the chip is increased at severalfold, and the read and write latencies are reduced about 40 percent.展开更多
SRAM(static random access memory)-based FPGA(field programmable gate array), owing to its large capacity, high performance, and dynamical reconfiguration, has become an attractive platform for So PC(system on programm...SRAM(static random access memory)-based FPGA(field programmable gate array), owing to its large capacity, high performance, and dynamical reconfiguration, has become an attractive platform for So PC(system on programmable chip) development. However, as the configuration memory and logic memory of the SRAM-based FPGA are highly susceptible to SEUs(single-event upsets) in deep space, it is a challenge to design and implement a highly reliable FPGA-based system for spacecraft, and no practical architecture has been proposed. In this paper, a new architecture for a reliable and reconfigurable FPGAbased computer in a highly critical GNC(guidance navigation and control) system is proposed. To mitigate the effect of an SEU on the system, multi-layer reconfiguration and multi-layer TMR(triple module redundancy) techniques are proposed, with a reliable reconfigurable real-time operating system(Space OS) managing the system level fault tolerance of the computer in the architecture. The proposed architecture for the reconfigurable FPGA-based computer has been implemented with COTS(commercial off the shelf) FPGA and has firstly been applied to the GNC system of a circumlunar return and reentry flight vehicle. The in-orbit results show that the proposed architecture is capable of meeting the requirements of high reliability and high availability, and can provide the expressive varying functionality and runtime flexibility for an FPGA-based GNC computer in deep space.展开更多
文摘A new hybrid FPGA architecture is proposed. The logic tile,which consists of a logic cluster and related connection boxes （CBs）, can be configured as either programmable logic arrays （PLAs） or look-up tables （LUTs）, This architecture can be classified as an AND-LUT array. PLAs are suitable for the implementation of high fan-in logic circuits, while LUTs are used to implement low fan-in logic circuits. As a result, the proposed hybrid FPGA architecture （HFA） is more flexible to improve logic density. Experiments based on MCNC benchmark circuits were performed in both the hybrid architecture and conventional LUT-based symmetrical FPGA architecture in term of area consumption. Preliminary results indicate that on average, the area is reduced by 46% using the new hybrid architecture.
文摘为开发高度集成的五指机器人灵巧手,提出了采用DSP(Digital Signal Processor)+FPGA(Field Programmable Gate Array)控制结构的模块化嵌入式手指控制系统设计方法。实现了采用单电流传感器检测全桥控制下相电流及相电流过流双保护。为解决手指DSP和FPGA之间如何稳定、高效通信的难题,结合先进先出FIFO(First In First Out)寄存器,设计了基于串行通信接口SCI(Serial Communications Interface)和RS485总线的多中断差分通信系统。实验证明,这种DSP+FPGA控制结构及模块化的设计,使得手指控制部分得以高度集成,同时DLR/HITII灵巧手获得很好的整体性能和稳定性。
文摘We develop a 3D bounded slice-surface grid （3D-BSSG） structure for representation and introduce the solution space smoothing technique to search for the optimal solution. Experiment results demonstrate that a 3D-BSSG structure based algorithm is very effective and efficient.
基金Supported by the National Natrual Science Foundation of China (No.60373044) and Knowl-edge Innovative Project of CAS (No.KSCX2-SW-233).
文摘The architecture of a BioAccel (internal code) chip for RNA secondary structure prediction is described in the letter. The system is based on a BioBus (internal code), whose distinguishing features are: Two separated control and data channels, and a slave-associated arbitration scheme. Two reference systems based on the AMBA AHB bus and Coreconnect bus are introduced to evaluate the performance of the system. The simulation results are attractive. The average communication bandwidth of the chip is increased at severalfold, and the read and write latencies are reduced about 40 percent.
基金supported by the Major Special Projects on National Medium and Long-term Science and Technology Development Planning
文摘SRAM(static random access memory)-based FPGA(field programmable gate array), owing to its large capacity, high performance, and dynamical reconfiguration, has become an attractive platform for So PC(system on programmable chip) development. However, as the configuration memory and logic memory of the SRAM-based FPGA are highly susceptible to SEUs(single-event upsets) in deep space, it is a challenge to design and implement a highly reliable FPGA-based system for spacecraft, and no practical architecture has been proposed. In this paper, a new architecture for a reliable and reconfigurable FPGAbased computer in a highly critical GNC(guidance navigation and control) system is proposed. To mitigate the effect of an SEU on the system, multi-layer reconfiguration and multi-layer TMR(triple module redundancy) techniques are proposed, with a reliable reconfigurable real-time operating system(Space OS) managing the system level fault tolerance of the computer in the architecture. The proposed architecture for the reconfigurable FPGA-based computer has been implemented with COTS(commercial off the shelf) FPGA and has firstly been applied to the GNC system of a circumlunar return and reentry flight vehicle. The in-orbit results show that the proposed architecture is capable of meeting the requirements of high reliability and high availability, and can provide the expressive varying functionality and runtime flexibility for an FPGA-based GNC computer in deep space.
