Although Alternate Parallel Receiver (APRX) could effectively improve the maximum demodulating rate of the receiver, its frequency domain processing module consumes a large amount of multiplication units when the numb...Although Alternate Parallel Receiver (APRX) could effectively improve the maximum demodulating rate of the receiver, its frequency domain processing module consumes a large amount of multiplication units when the number of parallel input channels is large, making it unsuitable for use on FPGA software defi ned radio platforms. This paper proposes an optimization scheme by introducing partitioned convolution and exploring the spectrum characteristic of the APRX input data, reducing the usage of multipliers greatly. After the optimization, the number of real multipliers used in the frequency-domain processing module of the 16-ary APRX is reduced from about 576 to 68, with little performance loss. This optimized APRX is fairly suitable for FPGA software defi ned radio platform applications.展开更多
A hardware/software field programmable gate array （FPGA）-based driver system was proposed and demonstrated for the KAF-39000 large area high resolution charge coupled device （CCD）. The requirements of the KAF-3900...A hardware/software field programmable gate array （FPGA）-based driver system was proposed and demonstrated for the KAF-39000 large area high resolution charge coupled device （CCD）. The requirements of the KAF-39000 driver system were analyzed. The structure of ＂microprocessor with application specific integrated circuit （ASIC） chips＂ was implemented to design the driver system. The system test results showed that dual channels of imaging analog data were obtained with a frame rate of 0.87frame/s. The frequencies of horizontal timing and vertical timing were 22.9MHz and 28.7kHz, respectively, which almost reached the theoretical value of 24 MHz and 30kHz, respectively.展开更多
基金This work was supported by the National Basic research Program of China (2007CB310600)the National Natural Science Foundation of China under Grants No. 60532070 and No. 60525107
文摘Although Alternate Parallel Receiver (APRX) could effectively improve the maximum demodulating rate of the receiver, its frequency domain processing module consumes a large amount of multiplication units when the number of parallel input channels is large, making it unsuitable for use on FPGA software defi ned radio platforms. This paper proposes an optimization scheme by introducing partitioned convolution and exploring the spectrum characteristic of the APRX input data, reducing the usage of multipliers greatly. After the optimization, the number of real multipliers used in the frequency-domain processing module of the 16-ary APRX is reduced from about 576 to 68, with little performance loss. This optimized APRX is fairly suitable for FPGA software defi ned radio platform applications.
文摘A hardware/software field programmable gate array （FPGA）-based driver system was proposed and demonstrated for the KAF-39000 large area high resolution charge coupled device （CCD）. The requirements of the KAF-39000 driver system were analyzed. The structure of ＂microprocessor with application specific integrated circuit （ASIC） chips＂ was implemented to design the driver system. The system test results showed that dual channels of imaging analog data were obtained with a frame rate of 0.87frame/s. The frequencies of horizontal timing and vertical timing were 22.9MHz and 28.7kHz, respectively, which almost reached the theoretical value of 24 MHz and 30kHz, respectively.
