基于关键翻转集合的极化码Fast-SSC-Flip译码算法

为了降低极化码快速简化串行抵消翻转(Fast-SSC-Flip)译码算法的候选翻转比特集合大小,减小搜索复杂度,该文提出一种基于关键翻转集合的极化码Fast-SSC-Flip译码算法。基于快速简化串行抵消(Fast-SSC)译码过程中首位译码错误信息比特有极大的概率落于关键集合(CS)中,以及Fast-SSC-Flip译码算法的候选比特均为码字比特,所提算法利用极化码的生成矩阵得到与CS中信息比特相应的码字比特,并用这些码字比特构建关键翻转集合(CFS)作为候选翻转比特集合。实验结果表明,在使用相同候选比特可靠性度量准则的前提下,在码长N=1024及码率R=0.5时,该文所提基于关键翻转集合的Fast-SSC-Flip译码算法相较于传统Fast-SSC-Flip算法在不损失译码性能的情况下,候选翻转集合大小显著降低;相较于新的快速简化串行抵消翻转(N-Fast-SSC-Flip)算法有相近的译码性能,但候选翻转集合至少缩小了77.93%。

一种高性能极化码Fast-SSC译码器设计

为了进一步降低无线通信系统中信道编码极化码Fast-SSC译码器的译码延迟和硬件资源消耗,本文提出了两种对Fast-SSC译码算法的优化方法,基于FPGA硬件实现了码长N=1024优化的Fast-SSC译码器.基于Fast-SSC译码树上的四种特殊结点Rate0、Rate1、Rep和SPC,提出分别以Rate0结点和Rep结点为基础进行组合型特殊结点的拓展,使译码树上的特殊结点类型由原来的四种增加至十种以上,进一步加快了搜索译码树的速度;提出存储器资源复用的方法,相同译码树深度的结点使用相同的存储空间.综合结果表明最大工作频率为169 MHz,译码延迟为1.71μs,数据吞吐率为599 Mbps,存储器消耗为14.8 Kbit,有效提升了Fast-SSC译码器的整体性能.

基于FPGA的高速Fast-SSC译码器测试系统

为了满足Polar码高性能测试时大数据量的要求,设计了一种针对Fast-SSC译码器的FPGA硬件测试平台,包含信源、信道编码器、调制器、信道、解调器、译码器和统计模块,采用Verilog在Altera Stratix V 5SGXEA7N2F45C2上实现,并采用PCIe接口与上位机进行通信。该平台对码长1 024、码率1/2的Polar码进行测试,结果表明测试频率为300 MHz、测试数据为1.4×1010位时,译码耗时仅为19.18 s。

基于关键简化集合的极化码SSRFSC翻转译码算法

为提高基于简化序列重复节点的快速串行抵消(SSRFSC)译码算法的译码性能,提出了基于关键简化集合(CSS)和简化序列重复(SSR)节点的CSS-SSR-Flip译码算法。所提算法首先选取SSR中最长重复(REP)节点的信息位作为候选比特(CB),从而构造了基于SSR的CSS;然后针对SSR节点的译码特点设计了相应的翻转度量和翻转准则,通过考虑SSR节点中重复序列和源节点对译码的影响来度量CB可靠性,在特定CB翻转时选择次优的重复序列完成SSR节点翻转操作。实验数据表明,当误帧率FER=10-3时,所提出的CSSSSR-Flip译码算法与传统的快速简化串行抵消翻转(Fast-SSC-Flip)译码算法相比能够获得超过0.1 dB的性能增益,且具有与新型Fast-SSC-Flip(New-Fast-SSC-Flip)译码算法相同的译码性能;与传统翻转集合大小K相比,CSS大小缩减最多达79.5%,与关键集合(CS)相比集合大小最多可缩减23.1%。

基于简化序列重复节点的极化码快速串行抵消译码算法

为了进一步降低串行抵消(SC)译码算法的译码时延,在序列重复(SR)节点的基础上,根据SR源节点的类型与译码复杂度,对不同类型的拓展类广义奇偶校验(EG-PC)节点进行分解、合并和简化,并使用快速简化串行抵消(Fast-SSC)译码对Rate-C节点进行裁剪处理,提出了基于简化SR节点的极化码快速SC译码算法(SSRFSC)。实验数据表明,在相近的译码性能下(在误帧率为10^(-3)时,约有0.1 dB的性能损失),与基于SR节点的快速SC(SRFSC)译码算法相比,所提算法的译码时延最多减少了28%;与Fast-SSC译码算法相比,译码时延最多减少了49%。

Improved Polar Decoder Utilizing Neural Network in Fast Simplified Successive-Cancellation Decoding

Polar codes using successive-cancellation decoding always suffer from high latency for its serial nature. Fast simplified successive-cancellation decoding algorithm improves the situation in theoretically but not performs well as expected in practical for the workload of nodes identification and the existence of many short blocks. Meanwhile, Neural network (NN) based decoders have appeared as potential candidates to replace conventional decoders for polar codes. But the exponentially increasing training complexity with information bits is unacceptable which means it is only suitable for short codes. In this paper, we present an improvement that increases decoding efficiency without degrading the error-correction performance. The long polar codes are divided into several sub-blocks, some of which can be decoded adopting fast maximum likelihood decoding method and the remained parts are replaced by several short codes NN decoders. The result shows that time steps the proposed algorithm need only equal to 79.8% of fast simplified successive-cancellation decoders require. Moreover, it has up to 21.2 times faster than successive-cancellation decoding algorithm. More importantly, the proposed algorithm decreases the hardness when applying in some degree.

RETRACTED: <i>Improved Polar Decoder Utilizing Neural Network in Fast Simplified Successive-Cancellation Decoding</i>

This article has been retracted to straighten the academic record. In making this decision the Editorial Board follows COPE's Retraction Guidelines. The aim is to promote the circulation of scientific research by offering an ideal research publication platform with due consideration of internationally accepted standards on publication ethics. The Editorial Board would like to extend its sincere apologies for any inconvenience this retraction may have caused. Please see the article page for more details. The full retraction notice in PDF is preceding the original paper which is marked "RETRACTED".