A Fault Current Limiting Hybrid DC Circuit Breaker

Due to the low impedance characteristic of the high voltage direct current(HVDC)grid,the fault current rises extremely fast after a DC-side fault occurs,and this phenomenon seriously endangers the safety of the HVDC grid.In order to suppress the rising speed of the fault current and reduce the current interruption requirements of the main breaker(MB),a fault current limiting hybrid DC circuit breaker(FCL-HCB)has been proposed in this paper,and it has the capability of bidirectional fault current limiting and fault current interruption.After the occurrence of the overcurrent in the HVDC grid,the current limiting circuit(CLC)of FCL-HCB is put into operation immediately,and whether the protected line is cut off or resumed to normal operation is decided according to the fault detection result.Compared with the traditional hybrid DC circuit breaker(HCB),the required number of semiconductor switches and the peak value of fault current after fault occurs are greatly reduced by adopting the proposed device.Extensive simulations also verify the effectiveness of the proposed FCL-HCB.

A Method on Analog Circuit Fault Diagnosis with Tolerance

In this paper, it is proved that the direction of the node-voltage difference vector, which is the difference between the node-voltage vector at faulty state and the one at the nominal state, is determined only by the location of the faulty clement in linear analog circuits. Considering that the direction of the node-voltage sensitivity vector is the same as the one of the node-voltage difference vector and also considering that the module of the node-voltage sensitivity vector presents the weight of the parameter of faulty element deviation relative to the voltage difference, fault dictionary is set up based on node-voltage sensitivity vectors. A decision algorithm is proposed concerned with both the location and the parameter difference of the faulty element. Single fault and multi-fault can be diagnosed while the circuit parameters deviate within the tolerance range of 10 %.

Stator Fault Diagnosis of Induction Motor Based on Discrete Wavelet Analysis and Neural Network Technique

A novel approach by introducing a statistical parameter to estimate the severity of incipient stator inter-turn short circuit(ITSC)faults in induction motors(IMs)is proposed.Determining the incipient ITSC fault and its severity is challenging for several reasons.The stator currents in the healthy and faulty cases are highly similar during the primary stage of the fault.Moreover,the conventional statistical parameters resulting from the analysis of fault signals do not consistently show a systematic variation with respect to the increase in fault intensity.The objective of this study is the early detection of incipient ITSC faults.Furthermore,it aims to determine the percentage of shorted turns in the faulty phase,which acts as an indicator for severe damage to the stator winding.Modeling of the motor in healthy and defective cases is performed using the Clarke Concordia transform.A discrete wavelet transform is applied to the motor currents using a Daubechies-8 wavelet.The statistical parameters L1 and L2 norms are computed for the detailed coefficients.These parameters are obtained under a variety of loads and defects to acquire the most accurate and generalized features related to the fault.Combining L1 and L2 norms creates a novel statistical parameter with notable characteristics to achieve the research aim.An artificial neural network-based back propagation algorithm is employed as a classifier to implement the classification process.The classifier output defines the percentage of defective turns with a high level of accuracy.The competency of the adopted methodology is validated via simulations and experiments.The results confirm the merits of the proposed method,with a classification test correctness of 95.29%.

Parallel Critical Path Tracing——A Fault Simulation Algorithm for Combinational Circuits

Critical path tracing,a fault simulation method for gate-level combinational circuits,is extended to theparallel critical path tracing for functional block-level combinational circuits.If the word length of the hostcomputer is m,then the parallel critical path tracing will be approximately m times faster than the originalone.

Efficient quantum arithmetic operation circuits for quantum image processing

Efficient quantum circuits for arithmetic operations are vital for quantum algorithms.A fault-tolerant circuit is required for a robust quantum computing in the presence of noise.Quantum circuits based on Clifford+T gates are easily rendered faulttolerant.Therefore,reducing the T-depth and T-Count without increasing the qubit number represents vital optimization goals for quantum circuits.In this study,we propose the fault-tolerant implementations for TR and Peres gates with optimized T-depth and T-Count.Next,we design fault-tolerant circuits for quantum arithmetic operations using the TR and Peres gates.Then,we implement cyclic and complete translations of quantum images using quantum arithmetic operations,and the scalar matrix multiplication.Comparative analysis and simulation results reveal that the proposed arithmetic and image operations are efficient.For instance,cyclic translations of a quantum image produce 50%T-depth reduction relative to the previous best-known cyclic translation.

A hybrid circuit breaker with fault current limiter circuit in a VSC-HVDC application

A conventional hybrid circuit breaker(HCB)is used to protect a voltage source converter-based high voltage direct current transmission system(VSC-HVDC)from a short circuit fault.With the increased converter capacity,the DC protection equipment also requires a regular upgrade.This paper adopts a novel type of HCB with a fault current limiter circuit(FCLC),and focuses on the responses of voltage and current during DC faults,which are associated with parameter selection.PSCAD/EMTDC based simulation of a three-terminal VSC-HVDC system confirms the effectiveness and value of HCB with FCLC,by using an equivalent circuit modelling approach.Laboratory experimental tests validate the simulation results.The peak fault current is reduced according to the current limiting inductor(CLI)increase,and can be isolated more quickly.By adopting parallel metal oxide arrester(MOA)with the main branch of HCB,voltage stresses across the breaker components decrease during transient and continuous operation,and less energy needs to be dissipated by the MOA.The remnant current for all cases is transmitted to power dissipating resis-tor(PDR)in the final stage,and the fault current is reduced to the lowest possible value.When the current from the main branch is transferred to the FCLC branch,transient voltage spikes occur,while smaller PDR is required to absorb current in the final stage.

k-NN based fault detection and classification methods for power transmission systems

This paper deals with two new methods,based on k-NN algorithm,for fault detection and classification in distance protection.In these methods,by finding the distance between each sample and its fifth nearest neighbor in a predefault window,the fault occurrence time and the faulty phases are determined.The maximum value of the distances in case of detection and classification procedures is compared with pre-defined threshold values.The main advantages of these methods are:simplicity,low calculation burden,acceptable accuracy,and speed.The performance of the proposed scheme is tested on a typical system in MATLAB Simulink.Various possible fault types in different fault resistances,fault inception angles,fault locations,short circuit levels,X/R ratios,source load angles are simulated.In addition,the performance of similar six well-known classification techniques is compared with the proposed classification method using plenty of simulation data.

Research on fast solid state DC breaker based on a natural current zero-crossing point

The DC fault characteristics of voltage source converter based high voltage direct current(VSC-HVDC)systems are analyzed in this paper.The phenomenon whereby the capacitor on DC side discharges quickly during a DC fault contributes to a large short-circuit fault current.Neither traditional DC breakers nor DC switches can cut off the fault current under this condition.A fast solid state DC breaker design method is proposed in this paper.This method is based on the fault current characteristics of the inverter in multi-terminal HVDC systems(MTDC),where a fault current appears at the natural zerocrossing point near the inverter.At this point,by coordinating the AC breakers near the rectifier,the DC breaker could reliably cut off the DC fault current and protect the system.A detailed model for this fast solid state DC breaker and its operation sequence are studied,based on this design method.Simulations modeling a five-terminal meshed DC grid and a fast DC breaker were carried out with PSCAD/EMTDC using this design method.The results from the simulations confirmed the validity of the design method.