Reliability evaluation of avionics system with imperfect fault coverage and propagated failure mechanisms

Fault tolerance designs are essential techniques for systems that require high levels of reliability,such as aircraft or spacecraft control system.Imperfect Fault Coverage(IFC)may lead to the failure of a system or subsystem even with adequate redundancy.Previous studies of IFC mostly concentrated on evaluating Coverage Factor(CF),whereas the system failure behaviors with IFC have rarely been involved.Failures that occur in low-layer may be covered by highlayer.However,if the coverage is imperfect,uncovered failure will have functional and physical impact on the system behavior.In this thesis,the failure behavior and reliability of IFC of multi-layer systems are studied and a Binary Decision Diagram(BDD)-based modeling and simulation method are proposed to evaluate system reliability.As a case,the failure behavior of an aero engine electronic controller with IFC is studied.The results show that the IFC may impact system behavior without taking the IFC into account,the system maintenance intervals may reduce,and thus the maintenance costs will increase.

Random-Like Testing of Very Large Scale Integration Circuit

A new approach to improve the test efficiency of random testing is presented in this paper. In conventional random testing, each test pattern is selected randomly regardless of the tests previously generated. This paper introduces the concept of random like testing. The method provided appears to have the same concepts as used in random testing,but actually takes an opposite way to it in order to improve the efficiency of random testing.In a random like testing sequence, the total distance among all test patterns is chosen to be maximal so that the fault sets detected by one test pattern are as different as possible from that detected by the tests previously applied. The procedure to construct a random like testing sequence (RLTS) is described in detail. Theorems to justify the effectiveness and usefulness of the procedure presented are developed. Experimental results on benchmark circuits as well as on other circuit are also given to evaluate the performance of the new approach.

Partition-based Low Power DFT Methodology for System-on-chips

This paper presents a partition-based Design-for- Test （DFT） technique to reduce the power consumption during scan-based testing. This method is based on partitioning the chip into several independent scan domains. By enabling the scan domains alternatively, only a fraction of the entire chip will be active at the same time, leading to low power consumption during test. Therefore, it will significantly reduce the possibility of Electronic Migration and Overheating. In order to prevent the drop of fault coverage, wrappers on the boundaries between scan domains are employed. This paper also presents a detailed design flow based on Electronics Design Automation （EDA） tools from Synopsy~ to implement the proposed test structure. The proposed DFT method is experimented on a state-of-theart System-ou-chips （SOC）. The simulation results show a significant reduction in both average and peak power dissipation without sacrificing the fault coverage and test time. This SOC has been taped out in TSMC and finished the final test m ADVANTEST.

On the Production Testing of Memristor Ratioed Logic (MRL) Gates

This paper focuses on the production testing of Memristor Ratioed Logic (MRL) gates. MRL is a family that uses memristors along with CMOS inverters to design logic gates. Two-input NAND and NOR gates are investigated using the stuck at fault model for the memristors and the five-fault model for the transistors. Test escapes may take place while testing faults in the memristors. Therefore, two solutions are proposed to obtain full coverage for the MRL NAND and NOR gates. The first is to apply scaled input voltages and the second is to change the switching threshold of the CMOS inverter. In addition, it is shown that test speed and order should be taken into consideration. It is proven that three ordered test vectors are needed for full coverage in MRL NAND and NOR gates, which is different from the order required to obtain 100% coverage in the conventional NAND and NOR CMOS designs.

C-Testable Motion Estimation Design for Video Coding Systems

A C-testable motion estimation （CTME） design to efficiently detect the faults in process elements （PEs） is presented. The goal of the CTME design is to offer high reliability for video coding systems. The proposed CTME was carried out by Verilog HDL （very high speed integrated circuit hardware description language） and synthesized with the TSMC （Taiwan Semiconductor Manufacturing Company） 0.18 μm CMOS technology. Logic simulation results show that the proposed CTME guarantees 100% fault coverage with only 8 sets of test patterns. Design verification and comparisons also demonstrate that the area overhead of the proposed CTME is about 4.8% with little delay penalty.

Testable Design and BIST Techniques for Systolic Motion Estimators in Transform Domain

Testable design techniques for systolic motion estimators based on M-testability conditions are proposed in this paper. The whole motion estimator can be viewed as a two-dimensional iterative logic array （ILA） of processing elements （PEs） and multiplying elements （MULs）. The functions of each PE and MUL are modified to be bijective to meet the M-testable conditions. The number of test patterns is 2^w, where w denotes the word length of a PE. The proposed testable design techniques are also suitable for built-in self-test implementation. According to experimental results, our approaches can achieve 99.27 % fault coverage. The area overhead is about 9 %. To verify our approaches, an experimental chip is also implemented.

DLJ:A Dynamic Line-Justification Algorithm for Test Generation

Line justification is a basic factor in affecting the efficiency of algorithms for test generation.The existence of reconvergent fanouts in the circuit under test resalts in backtracks in the process of line justification.In order to reduce the number of backtracks and shorten the processing time between backtracks,we present a new algorithm called DLJ(dynamic line justification)in which two techniques are employed.1.A cost function called“FOCOST”is proposed as heuristic information to represent the cost of justifying a certain line.When the relations among the lines being justified are“and”,the line having the highest FOCOST should be chosen.When the relations are“or”,the line having the lowest FOCOST should be chosen.The computing of the FOCOST of lines is very simple.2. Disjoint justification cubes dynamically generated to perform backtracks make the backtrack number of the algorithm minimal.When the backtrace with cube C_1 does not yield a solution,the next cube to be chosen is C′_2=C_2-{C_1,C_2}.Experimental results demonstrate that the combination of the two techniques effectively reduces the backtracks and accelerates the test generation.