Low overhead design-for-testability for scan-based delay fault testing

An efficient design-for-testability （DFT） technique is proposed to achieve low overhead for scan-based delay fault testing. Existing techniques for delay test such as skewed-load or broadside make the test generation process complex and produce lower coverage for scan-based designs as compared with non-scan designs, whereas techniques such as enhanced-scan test can make the test easy but need an extra holding latch to add substantial hardware overhead. A new tri-state holding logic is presented to replace the common holding latch in enhanced-scan test to get a substantial low hardware overhead. This scheme can achieve low delay overhead by avoiding the holding latch on the critical timing scan path. What＇s more, this method can also keep the state and signal activity in the combinational circuit from the scan during data scan-in operation to reduce the power dissipation. Experiment results on a set of ISCAS89 benchmarks show the efficiency of the proposed scheme.

NHPP-based software reliability model considering testing effort and multivariate fault detection rate

In recent decades,many software reliability growth models（SRGMs） have been proposed for the engineers and testers in measuring the software reliability precisely.Most of them is established based on the non-homogeneous Poisson process（NHPP）,and it is proved that the prediction accuracy of such models could be improved by adding the describing of characterization of testing effort.However,some research work indicates that the fault detection rate（FDR） is another key factor affects final software quality.Most early NHPPbased models deal with the FDR as constant or piecewise function,which does not fit the different testing stages well.Thus,this paper first incorporates a multivariate function of FDR,which is bathtub-shaped,into the NHPP-based SRGMs considering testing effort in order to further improve performance.A new model framework is proposed,and a stepwise method is used to apply the framework with real data sets to find the optimal model.Experimental studies show that the obtained new model can provide better performance of fitting and prediction compared with other traditional SRGMs.

Design and Test of Multibus Adapter System on a Chip for Fault Tolerant Computer Systems

In order to improve the system reliability and performance and to reduce the system cost, volume and weight, we have designed, fabricated and tested the multibus adapter system of a trimodular redundant fault tolerant computer system on a single chip of 5000 gate CMOS gate array. The design, fabrication and test of this single chip system will be discussed..

Transmission cable fault detector based on waveform reconstruction

In order to improve the accuracy of cable fault position location at a low cost and make the testing results intuitive, a cable fault detector based on wave form reconstruction is designed. In this detector, the cable fault position is located based on the time-domain pulse reflection （TDR） principle. A pulse waveform is injected in the tested cable, and a high-speed comparator with changeable reference voltages is used to binarize the test pulse waveform to a binary sequence on a certain voltage. Through scanning the reference voltage in a full voltage range, multi-sequences are acquired to reconstruct the pulse waveform transmission in the cable, and then the pulse attenuation feature, electrical open circuit fault, electrical short circuit fault, and the fault position of the cable are diagnosed. Experimental results show that the designed cable fault detector can determine the fault type and its position of the cable being tested, and the testing results are intuitive.

Constraint-induced movement therapy promotes motor function recovery and downregulates phosphorylated extracellular regulated protein kinase expression in ischemic brain tissue of rats

Motor function impairment is a common outcome of stroke.Constraint-induced movement therapy（CIMT）involving intensive use of the impaired limb while restraining the unaffected limb is widely used to overcome the effects of＇learned non-use＇and improve limb function after stroke.However,the underlying mechanism of CIMT remains unclear.In the present study,rats were randomly divided into a middle cerebral artery occlusion（model）group,a CIMT＋model（CIMT）group,or a sham group.Restriction of the affected limb by plaster cast was performed in the CIMT and sham groups.Compared with the model group,CIMT significantly improved the forelimb functional performance in rats.By western blot assay,the expression of phosphorylated extracellular regulated protein kinase in the bilateral cortex and hippocampi of cerebral ischemic rats in the CIMT group was significantly lower than that in the model group,and was similar to sham group levels.These data suggest that functional recovery after CIMT may be related to decreased expression of phosphorylated extracellular regulated protein kinase in the bilateral cortex and hippocampi.

Improved Control Strategy for Carbonized Cable Preparation in Low-voltage Arc Fault Test

Outdated testing methods hinder the success rate of carbonized cable preparation in low-voltage arc fault tests,leading to incomplete tests and high failure rates.To address this issue,we finely categorized the preparation results of carbonized cable specimens by analyzing the experimental phenomena during the carbonization process and assessing the impact of high-voltage energization time on the outcomes,presenting a process control strategy aimed at optimizing the preparation results of carbonized cable specimens.This method utilizes three periodic moving algorithms(root-mean-square,average,and shoulder percentage)to classify the cable specimens into four preparation categories:open-circuit carbonization,under-carbonization,short-circuit carbonization,and successful carbonization.The high-voltage energization time during carbonization or secondary carbonization was adjusted to optimize the preparation of the carbonized cables by considering different discrimination outcomes.Finally,the proposed method was tested on a purpose-built carbonized cable experimental platform,which confirmed its effectiveness in differentiating the preparation outcomes of the carbonized cable specimens and improving the success rate of the carbonized cable preparation.The proposed method has significant potential for application in low-voltage arc fault test systems.

Test sequencing problem arising at the design stage for reducing life cycle cost

Previous test sequencing algorithms only consider the execution cost of a test at the application stage. Due to the fact that the placement cost of some tests at the design stage is considerably high compared with the execution cost, the sequential diagnosis strategy obtained by previous methods is actually not optimal from the view of life cycle. In this paper, the test sequencing problem based on life cycle cost is presented. It is formulated as an optimization problem, which is non-deterministic polynomial-time hard （NP-hard）. An algorithm and a strategy to improve its computational efficiency are proposed. The formulation and algorithms are tested on various simulated systems and comparisons are made with the extant test sequencing methods. Application on a pump rotational speed control （PRSC） system of a spacecraft is studied in detail. Both the simulation results and the real-world case application results suggest that the solution proposed in this paper can significantly reduce the life cycle cost of a sequential fault diagnosis strategy.

A Fault Sample Simulation Approach for Virtual Testability Demonstration Test

Virtual testability demonstration test has many advantages,such as low cost,high efficiency,low risk and few restrictions.It brings new requirements to the fault sample generation.A fault sample simulation approach for virtual testability demonstration test based on stochastic process theory is proposed.First,the similarities and differences of fault sample generation between physical testability demonstration test and virtual testability demonstration test are discussed.Second,it is pointed out that the fault occurrence process subject to perfect repair is renewal process.Third,the interarrival time distribution function of the next fault event is given.Steps and flowcharts of fault sample generation are introduced.The number of faults and their occurrence time are obtained by statistical simulation.Finally,experiments are carried out on a stable tracking platform.Because a variety of types of life distributions and maintenance modes are considered and some assumptions are removed,the sample size and structure of fault sample simulation results are more similar to the actual results and more reasonable.The proposed method can effectively guide the fault injection in virtual testability demonstration test.

Model-Based Embedded Compiled Software Fault Positioning

Software fault positioning is one of the most effective activities in program debugging. In this paper, we propose a model-based fault positioning method to detect the faults of embedded program without source code. The system takes the machine code of embedded software as input and translates the code into high-level language C with the software reverse engineering program. Then, the static analysis on the high-level program is taken to obtain a control flow graph（CFG）, which is denoted as a node-tree and each node is a basic block. According to the faults found by the field testing, we construct a fault model by extracting the features of the faulty code obtained by ranking the Ochiai coefficient of basic blocks. The model can be effectively used to locate the faults of the embedded program. Our method is evaluated on ST chips of the smart meter with the corresponding source code. The experiment shows that the proposed method has an effectiveness about 87% on the fault detection.