A New Design Method for Variable Digital Filter Based on Field Programmable Gate Array(FPGA)

In order to obtain variable characteristics,the digital filter's type,number of taps and coefficients should be changed constantly such that the desired frequency-domain characteristics can be obtained.This paper proposes a method for self-programmable variable digital filter(VDF) design based on field programmable gate array(FPGA).We implement a digital filter system by using custom embedded micro-processor,programmable finite impulse response(P-FIR) macro module,coefficient-loader,clock manager and analog/digital(A/D) or digital/analog(D/A) controller and other modules.The self-programmable VDF can provide the best solution for realization of digital filter algorithms,which are the low-pass,high-pass,band-pass and band-stop filter algorithms with variable frequency domain characteristics.The design examples with minimum 1 to maximum 32 taps FIR filter,based on Modelsim post-routed simulation and onboard running on XUPV5-LX110T,are provided to demonstrate the effectiveness of the proposed method.

一款基于新型Field Programmable Gate Array芯片的投影仪梯形校正系统研究与实现

投影设备配备的梯形校正普遍存在校正范围小,画面的一些线条和字符边缘会出现毛刺和不平滑现象,矫正效果不理想.如果采用通用的图像处理芯片和复杂的算法,可以解决上述问题,但又会导致成本急剧上升.为了解决上述矛盾,提出一种基于FPGA(Field Programmable Gate Array)芯片的新型梯形校正实现方案,解决了校正范围与锯齿失真的矛盾问题,并为进一步成为芯片级产品铺平了道路.图像处理采用kaiser窗函数和sinc函数相结合的方法进行插值,这样的滤波器改善了旁瓣抑制,具有较好的通带性能.介绍了梯形失真的产生和校正原理,提出了利用FPGA芯片XC3S400作为核心图像处理单元的梯形校正系统的硬件和软件实现,说明了该芯片结构、功能及特性,最后提供了校正的效果图.

Synthesis of Nonlinear Control of Switching Topologies of Buck-Boost Converter Using Fuzzy Logic on Field Programmable Gate Array (FPGA)

An intelligent fuzzy logic inference pipeline for the control of a dc-dc buck-boost converter was designed and built using a semi-custom VLSI chip. The fuzzy linguistics describing the switching topologies of the converter was mapped into a look-up table that was synthesized into a set of Boolean equations. A VLSI chip–a field programmable gate array (FPGA) was used to implement the Boolean equations. Features include the size of RAM chip independent of number of rules in the knowledge base, on-chip fuzzification and defuzzification, faster response with speeds over giga fuzzy logic inferences per sec (FLIPS), and an inexpensive VLSI chip. The key application areas are: 1) on-chip integrated controllers;and 2) on-chip co-integration for entire system of sensors, circuits, controllers, and detectors for building complete instrument systems.

Implementation of Synchronization Technology in Orthogonal Frequency Division Multiplex System Based on Field Programming Gate Array

In this paper,analyzed is the symbol synchronization algorithm in orthogonal frequency division multiplex(OFDM)system,and accomplished are the hardware circuit design of coarse and elaborate synchronization algorithms.Based on the analysis of coarse and elaborate synchronization algorithms,multiplexed are,the module accumulator,division and output judgement,which can evidently save the hardware resource cost.The analysis of circuit sequence and wave form simulation of the design scheme shows that the proposed method efficiently reduce system resources and power consumption.

A novel fuzzy logic direct torque controller for a permanent magnet synchronous motor with a field programmable gate array

A high-performance digital servo system built on the platform of a field programmable gate array (FPGA),a fully digitized hardware design scheme of a direct torque control (DTC) and a low speed permanent magnet synchronous motor (PMSM) is proposed. The DTC strategy of PMSM is described with Verilog hardware description language and is employed on-chip FPGA in accordance with the electronic design automation design methodology. Due to large torque ripples in low speed PMSM,the hysteresis controller in a conventional PMSM DTC was replaced by a fuzzy controller. This FPGA scheme integrates the direct torque controller strategy,the time speed measurement algorithm,the fuzzy regulating technique and the space vector pulse width modulation principle. Experimental results indicate the fuzzy controller can provide a controllable speed at 20 r min-1 and torque at 330 N m with satisfactory dynamic and static performance. Furthermore,the results show that this new control strategy decreases the torque ripple drastically and enhances control performance.

Fault Prediction and Diagnosis of Warship Equipment Field Programmable Gate Array Software

In order to solve the current high failure rate of warship equipment field programmable gate array( FPGA) software,fault detection is not timely enough and FPGA detection equipment is expensive and so on. After in-depth research,this paper proposes a warship equipment FPGA software based on Xilinx integrated development environment( ISE) and ModelSim software.Functional simulation and timing simulation to verify the correctness of the logic design of the FPGA,this method is very convenient to view the signal waveform inside the FPGA program to help FPGA test engineers to achieve FPGA fault prediction and diagnosis. This test method has important engineering significance for the upgrading of warship equipment.

Implimentations of SIMD machine using programmable gate array

Field Programmable Gate Array(FPGA) and Single Instruction Multiple Data(SIMD) processing array share many architecture features. In both architectures, an array is employed to provide high speed computation. In this paper we show that the implementation of a Single Instruction Multiple Data (SIMD) machine the ABC 90 using the Field Programmable Gate Array (FPGA) is not completely suitable because of its characteristics. The comparison between the programmable gate arrays show that, they have many architectures features in common. Within this framework, we examine the differences and similarities between these array structures and touch upon techniques and lessons which can be done between these architectures in order to choose the appropriate Programmable gate array to implement a general purpose parallel computer. In this paper we introduce the principal of the Dynamically Programmable Date Array(DPGA) which combines the best feature of the FPGA and the SIMD arrays into a single array architecture. By the same way we show that the DPGA is more appropriate then the FPGA for wiring, hardwiring the general purpose parallel computers: SIMD and its implementation.

MIXED-GRAINED CMOS FIELD PROGRAMMABLE ANALOG ARRAY FOR SMART SENSORY APPLICATIONS

The drive towards shorter design cycles for analog integrated circuits has given impetus to the development of Field Programmable Analog Arrays(FPAAs),which are the analogue counterparts of Field Programmable Gate Arrays(FPGAs).In this paper,we present a new design methodology which using FPAA as a powerful analog front-end processing platform in the smart sensory microsystem.The proposed FPAA contains 16 homogeneous mixed-grained Configurable Analog Blocks(CABs) which house a variety of processing elements especially the proposed fine-grained Core Configurable Amplifiers(CCAs).The high flexible CABs allow the FPAA operating in both continuous-time and discrete-time approaches suitable to support variety of sensors.To reduce the nonideal parasitic effects and save area,the fat-tree interconnection network is adopted in this FPAA.The functionality of this FPAA is demonstrated through embedding of voltage and capacitive sensor signal readout circuits and a configurable band pass filter.The minimal detectable voltage and capacitor achieves 38 uV and 8.3 aF respectively within 100 Hz sensor bandwidth.The power consumption comparison of CCA in three applications shows that the FPAA has high power efficiency.And the simulation results also show that the FPAA has good tolerance with wide PVT variations.

FPGA implementation of bit-stream neuron and perceptron based on sigma delta modulation

To solve the excessive huge scale problem of the traditional multi-bit digital artificial neural network（ANN） hardware implementation methods,a bit-stream ANN hardware implementation method based on sigma delta（ΣΔ） modulation is presented.The bit-stream adder,multiplier,threshold function unit and fully digital ΣΔ modulator are implemented in a field programmable gate array（FPGA）,and these bit-stream arithmetical units are employed to build the bit-stream artificial neuron.The function of the bit-stream artificial neuron is verified through the realization of the logic function and a linear classifier.The bit-stream perceptron based on the bit-stream artificial neuron with the pre-processed structure is proved to have the ability of nonlinear classification.The FPGA resource utilization of the bit-stream artificial neuron shows that the bit-stream ANN hardware implementation method can significantly reduce the demand of the ANN hardware resources.

基于FPGA的新能源低压直流配电系统暂态实时仿真研究

对新能源低压直流配电系统开展暂态实时仿真研究对优化其运行控制具有重要作用。由于现场可编程门阵列(FPGA)内部集成了大量具有不同功能的电路,FPGA正成为电力系统暂态实时仿真领域主要的计算载体之一。该文面向新能源低压直流配电系统的暂态实时仿真需求,开发了一种基于FPGA的包含小型分布式风力发电、光伏发电以及蓄电池储能单元的新能源低压直流配电系统暂态实时仿真器。首先,研究构建了分布式发电单元和典型控制回路的计算模块,利用FPGA的并行计算特性并结合“算法-结构-有效匹配(AAA)”理念建立了底层模块串并联混合求解结构;然后,在节点分析法的框架下,建立了一种结合矩阵LDU分解和有向无环图(DAG)的电气系统节点电导矩阵并行求解方法;最后,在建立电气系统与控制系统并行求解架构的基础上,开发了一种基于FPGA的新能源低压直流配电系统暂态实时仿真器,通过将其仿真结果与PSCAD/EMTDC离线仿真平台的计算结果进行对比,验证了所开发暂态实时仿真器的有效性和准确性。

基于FPGA的PMLSM三矢量模型预测电流控制IP核设计及硬件在环验证

为了提升永磁直线同步电机(PMLSM)电流控制的稳态性能和执行速度,同时降低资源消耗,基于现场可编程门阵列(FPGA)设计了一个三矢量模型预测电流控制(TV-MPCC)知识产权(IP)核,并利用FPGA在环可视化验证方法,建立了一个PMLSM的TV-MPCC IP核验证系统。通过Simulink对TV-MPCC策略进行算法级仿真,并优化了基本电压矢量的作用顺序;采用并行与资源共享硬件优化技术设计并封装了一个TV-MPCC IP核,并对其进行了功能仿真;将设计部署在FPGA芯片XC7Z020CLG400-2上,利用FPGA在环可视化验证平台进行实验研究。结果表明,TV-MPCC策略下d、q轴电流跟踪误差和电流脉动均降低90%以上;FPGA工作在100 MHz下,实现一次算法的时间为0.62μs,仅为软件PyCharm执行时间的0.414%。

基于FPGA的小信号高精度采集系统设计

针对激光打靶实验中对靶心温度和光照强度的高精度采集需求,以现场可编程门阵列(FPGA)为核心,实现了一种多路高精度采集系统。系统通过对信号源输出的模拟K型热电偶的信号进行采集,将采集的信号作为样本,估计出每个通道的增益误差和偏移量,借助最小二乘法得到每个通道修正误差所需要的系数,最后再通过配置AD7768实现对误差的修正。实验结果表明:在修正前增益误差为0.207 8%,修正之后增益误差为0.002 7%,采用修正方法后,实现采集误差在10μV以内,有效地提高了系统对微小信号的采集精度。

基于FPGA的两阶段配电网拓扑实时辨识算法

对配电网拓扑进行准确的实时辨识是电力系统安全稳定运行的基础,但随着新能源的接入以及配电网规模不断增大,配电网拓扑结构的动态变化愈加频繁且难以辨识。然而,现有配电网拓扑辨识算法所使用的历史数据需要人工对其进行拓扑标注,且拓扑辨识时间长,难以实现配电网拓扑实时辨识。因此,文中提出了一种基于现场可编程逻辑门阵列(FPAG)的两阶段配电网拓扑结构实时辨识算法。该算法不需要预先给出配电网拓扑类别的数量,即可对已有历史数据进行相应的拓扑标注及分类,并且基于FPGA实现了对配电网拓扑的实时辨别。该算法分为2个阶段:第1阶段采用变分贝叶斯高斯混合模型,对已有历史数据进行相应的拓扑标注及分类;第2阶段采用麻雀搜索算法,使得支持向量机快速收敛得到最优参数,以实现对配电网拓扑结构的精准辨识。基于该算法,利用FPGA并行架构以及高速高密度特性建立了实时拓扑结构辨识平台。最后,通过算例分析验证了所提辨识方法的有效性和优越性。

Implementation of encoder and decoder for LDPC codes based on FPGA

This paper proposes a parallel cyclic shift structure of address decoder to realize a high-throughput encoding and decoding method for irregular-quasi-cyclic low-density parity-check(IR-QC-LDPC)codes,with a dual-diagonal parity structure.A normalized min-sum algorithm(NMSA)is employed for decoding.The whole verification of the encoding and decoding algorithm is simulated with Matlab,and the code rates of 5/6 and 2/3 are selected respectively for the initial bit error ratio as 6%and 1.04%.Based on the results of simulation,multi-code rates are compatible with different basis matrices.Then the simulated algorithms of encoder and decoder are migrated and implemented on the field programmable gate array(FPGA).The 183.36 Mbps throughput of encoder and the average 27.85 Mbps decoding throughput with the initial bit error ratio 6%are realized based on FPGA.

基于FPGA的卷积神经网络和视觉Transformer通用加速器

针对计算机视觉领域中基于现场可编程逻辑门阵列(FPGA)的传统卷积神经网(CNN)络加速器不适配视觉Transformer网络的问题,该文提出一种面向卷积神经网络和Transformer的通用FPGA加速器。首先,根据卷积和注意力机制的计算特征,提出一种面向FPGA的通用计算映射方法;其次,提出一种非线性与归一化加速单元,为计算机视觉神经网络模型中的多种非线性和归一化操作提供加速支持;然后,在Xilinx XCVU37P FPGA上实现了加速器设计。实验结果表明,所提出的非线性与归一化加速单元在提高吞吐量的同时仅造成很小的精度损失,ResNet-50和ViT-B/16在所提FPGA加速器上的性能分别达到了589.94 GOPS和564.76 GOPS。与GPU实现相比,能效比分别提高了5.19倍和7.17倍;与其他基于FPGA的大规模加速器设计相比,能效比有明显提高,同时计算效率较对比FPGA加速器提高了8.02%~177.53%。

一种FPGA⁃TDC防气泡误差编码器设计

在设计基于现场可编程门阵列(FPGA)的时间数字转换器(TDC)时,时钟偏斜等因素产生的气泡误差会造成抽头延迟链(TDL)中的延迟单元失效,导致TDC的分辨率变差。提出了一种防气泡误差编码器,通过统计抽头延迟链中发生变化的抽头个数,该编码器使抽头延迟链跳变顺序按照时间顺序映射,从而消除气泡误差的影响。利用Xilinx Virtex UltraScale+FPGA对该防气泡误差编码器的有效性进行验证,使用该编码器后,基于双端采样法的抽头延迟链TDC分辨率由3.18 ps提升至1.76 ps。实验结果表明,所提出的防气泡误差编码器能够解决气泡误差导致的延迟单元失效的问题,避免分辨率的损失。

FPGA-Based Efficient Programmable Polyphase FIR Filter

The modelling, design and implementation of a high-speed programmable polyphase finite impulse response (FIR) filter with field programmable gate array (FPGA) technology are described. This FIR filter can run automatically according to the programmable configuration word including symmetry/asymmetry, odd/even taps, from 32 taps up to 256 taps. The filter with 12 bit signal and 12 bit coefficient word-length has been realized on a Xilinx VirtexⅡ-v1500 device and operates at the maximum sampling frequency of (160 MHz.)

基于FPGA的软硬件协同纠删码编码加速方案

纠删码容错技术已广泛应用于分布式存储系统,相较于多副本容错技术能显著降低数据存储成本,并且具有更高的数据通信可靠性和安全性,但在数据存储过程中不可避免地会引入额外的计算开销并增加编码时延,导致数据写入吞吐量降低。针对该问题,提出一种基于现场可编程门列阵(FPGA)的纠删码编码加速方案。首先,利用FPGA的高速并行计算优势对纠删码算法进行硬件加速,并实现并行处理和时序优化。然后,针对上位机与FPGA之间因传输速率和处理速率不一致造成内存中的数据溢出问题,在FPGA上拓展了片外DDR3接口用于数据缓存,提高了通信可靠性,并利用DDR3的随机存取特点实现对数据块的分片。最后,设计基于FPGA的纠删码编码硬件加速架构进行实验验证。实验结果表明,与主流Jerasure 2.0开源纠删码库相比,该方案的数据写入吞吐量提升了2.7~93.0倍,尤其对于小文件的编码写入性能提升更为显著。

基于FPGA误差可控的浮点运算加速器研究

浮点运算是高性能计算(HPC)领域的基础运算。在大数据与云计算的背景下,高性能计算平台需要处理的数据量与日俱增,而且浮点数的舍入误差在大规模、长时程的运算中会产生累积,因此,在提升浮点运算性能的同时保证计算结果的可靠性非常重要。利用现场可编程门阵列(FPGA)可编程、低功耗、灵活性强的特点,针对含复杂单项运算的浮点多项式设计一种浮点运算加速器。基于无误差变换的思想,通过计算得出舍入误差值,将其补偿到浮点数值上,从而实现误差可控。采用异步并行的方式实现运算加速,并通过构建CPU-FPGA平台最大化地利用计算资源,保证计算任务执行的高效性。数据测试结果表明:在不限制对称性下的数值相对论模拟运算中,该加速器在200 MHz的主频下可达到91.85 MFLOPs的峰值性能;与Intel i76700K CPU运行最大线程数的性能相比,该加速器实现了50.54的加速比,并在该条件下获得了平均53.6%的精确结果百分比以及更低的相对误差,表明其具备较高的可靠性。

Implementation of a kind of FPGA-based binary phase coded radar signal processor architecture

A flexible field programmable gate array based radar signal processor is presented. The radar signal processor mainly consists of five functional modules： radar system timer, binary phase coded pulse compression（PC）, moving target detection （MTD）, constant false alarm rate （CFAR） and target dots processing. Preliminary target dots information is obtained in PC, MTD, and CFAR modules and Nios I! CPU is used for target dots combination and false sidelobe target removing. Sys- tem on programmable chip （SOPC） technique is adopted in the system in which SDRAM is used to cache data. Finally, a FPGA-based binary phase coded radar signal processor is realized and simula- tion result is given.