In this study, we examine how the quantum circuit of the Advanced Encryption Standard(AES) can be optimized from two aspects, i.e., number of qubits and T-depth. To reduce the number of qubits, we present three kinds ...In this study, we examine how the quantum circuit of the Advanced Encryption Standard(AES) can be optimized from two aspects, i.e., number of qubits and T-depth. To reduce the number of qubits, we present three kinds of improved quantum circuits of S-box for different phases in the AES. We found that the number of qubits in the round function can be decreased by introducing the circuit sending |a> to |S(a)>. As a result, compared with the previous quantum circuits where 400/640/768 qubits are required,our circuits of AES-128/-192/-256 only require 270/334/398 qubits. To reduce the T-depth, we propose a new circuit of AES's S-box with a T-depth of 4. Accordingly, the T-depth of our AES-128/-192/-256 quantum circuits become 80/80/84 instead of120/120/126 in a previous study.展开更多
The recent development of microelectronics techniques and advances in wireless communications have made it feasible to design low-cost, low-power, multifunctional and intelligent sensor nodes for wireless sensor netwo...The recent development of microelectronics techniques and advances in wireless communications have made it feasible to design low-cost, low-power, multifunctional and intelligent sensor nodes for wireless sensor networks （WSN）. The design challenges for an efficient WSN mainly lie in two issues： power and security. The Rijindael algorithm is a candidate algorithm for encrypting data in WSN. The SubByte （S-box） transformation is the main building block of the Rijindael algorithm. It dominates the hardware complexity and power consumption of the Rijindael cryptographic engine. This article proposes a clock-less hardware implementation of the S-box. In this S-box, l） The composite field arithmetic in GF（（2^4））2 was used to implement the compact datapath circuit; 2） A high-efficiency latch controller was attained by utilizing the four-phase micropipeline. The presented hardware circuit is an application specific integrated circuit （ASIC） on 0.25 μm complementary mental oxide semiconductor （CMOS） process using three metal layers. The layout simulation results show that the proposed S-box offers low-power consumption and high speed with moderate area penalty. This study also proves that the clock-less design methodology can implement high- performance cryptographic intellectual property （IP） core for the wireless sensor node chips.展开更多
基金supported by the National Natural Science Foundation of China (Grant Nos. 61972048, and 61976024)Beijing Natural Science Foundation (Grant No. 4222031)。
文摘In this study, we examine how the quantum circuit of the Advanced Encryption Standard(AES) can be optimized from two aspects, i.e., number of qubits and T-depth. To reduce the number of qubits, we present three kinds of improved quantum circuits of S-box for different phases in the AES. We found that the number of qubits in the round function can be decreased by introducing the circuit sending |a> to |S(a)>. As a result, compared with the previous quantum circuits where 400/640/768 qubits are required,our circuits of AES-128/-192/-256 only require 270/334/398 qubits. To reduce the T-depth, we propose a new circuit of AES's S-box with a T-depth of 4. Accordingly, the T-depth of our AES-128/-192/-256 quantum circuits become 80/80/84 instead of120/120/126 in a previous study.
基金the Hi-Tech Research and Development Program of China（2006AA01Z226）the Scientific Research Foundation of Huazhong University of Science and Technology（2006Z001B)the Natural Science Foundation of Hubei（2006ABA080）.
文摘The recent development of microelectronics techniques and advances in wireless communications have made it feasible to design low-cost, low-power, multifunctional and intelligent sensor nodes for wireless sensor networks （WSN）. The design challenges for an efficient WSN mainly lie in two issues： power and security. The Rijindael algorithm is a candidate algorithm for encrypting data in WSN. The SubByte （S-box） transformation is the main building block of the Rijindael algorithm. It dominates the hardware complexity and power consumption of the Rijindael cryptographic engine. This article proposes a clock-less hardware implementation of the S-box. In this S-box, l） The composite field arithmetic in GF（（2^4））2 was used to implement the compact datapath circuit; 2） A high-efficiency latch controller was attained by utilizing the four-phase micropipeline. The presented hardware circuit is an application specific integrated circuit （ASIC） on 0.25 μm complementary mental oxide semiconductor （CMOS） process using three metal layers. The layout simulation results show that the proposed S-box offers low-power consumption and high speed with moderate area penalty. This study also proves that the clock-less design methodology can implement high- performance cryptographic intellectual property （IP） core for the wireless sensor node chips.
