WT8.BZ]A new quasi 2-dimensional analytical approach to predicting the ring voltage,edge peak fields and optimal spacing of the planar junction with a single floating field limiting ring structure has been proposed,ba...WT8.BZ]A new quasi 2-dimensional analytical approach to predicting the ring voltage,edge peak fields and optimal spacing of the planar junction with a single floating field limiting ring structure has been proposed,based on the cylindrical symmetric solution and the critical field concept.The effects of the spacing and reverse voltage on the ring junction voltage and edge peak field profiles have been analyzed.The optimal spacing and the maximum breakdown voltage of the structure have also been obtained.The analytical results are in excellent agreement with that obtained from the 2-D device simulator,MEDICI and the reported result,which proves the presented model valid.展开更多
A vertical sandwich deep trench with a field limiting ring is proposed to improve the breakdown voltage of power devices and high voltage devices.Simulation result shows that nearly 100% breakdown voltage of the plane...A vertical sandwich deep trench with a field limiting ring is proposed to improve the breakdown voltage of power devices and high voltage devices.Simulation result shows that nearly 100% breakdown voltage of the plane junction can be realized.展开更多
A novel thin drift region device with heavily doped N＋ rings embedded in the substrate is reported, which is called the field limiting rings in substrate lateral double-diffused MOS transistor （SFLR LDMOS）. In the ...A novel thin drift region device with heavily doped N＋ rings embedded in the substrate is reported, which is called the field limiting rings in substrate lateral double-diffused MOS transistor （SFLR LDMOS）. In the SFLR LDMOS, the peak of the electric field at the main junction is reduced due to the transfer of the voltage from the main junction to other field limiting ring junctions, so the vertical electric field is improved significantly. A model of the breakdown voltage is developed, from which optimal spacing is obtained. The numerical results indicate that the breakdown voltage of the device proposed is increased by 76% in comparison to that of the conventional LDMOS.展开更多
This paper describes the successful fabrication of 4H-SiC junction barrier Schottky （JBS） rectifiers with a linearly graded field limiting ring （LG-FLR）. Linearly variable ring spacings for the FLR termination are...This paper describes the successful fabrication of 4H-SiC junction barrier Schottky （JBS） rectifiers with a linearly graded field limiting ring （LG-FLR）. Linearly variable ring spacings for the FLR termination are applied to improve the blocking voltage by reducing the peak surface electric field at the edge termination region, which acts like a variable lateral doping profile resulting in a gradual field distribution. The experimental results demonstrate a breakdown voltage of 5 kV at the reverse leakage current density of 2 mA/cm2 （about 80% of the theoretical value）. Detailed numerical simulations show that the proposed termination structure provides a uniform electric field profile compared to the conventional FLR termi- nation, which is responsible for 45% improvement in the reverse blocking voltage despite a 3.7% longer total termination length.展开更多
对常用的场限环(FLR)和正、负斜角终端结构的耐压机理进行了简要分析,讨论了其结构参数的优化方法。基于GTR台面终端结构,在功率M O SFET中引入了一种类似的沟槽负斜角终端结构。利用ISE软件对其耐压机理和击穿特性进行了模拟与分析。...对常用的场限环(FLR)和正、负斜角终端结构的耐压机理进行了简要分析,讨论了其结构参数的优化方法。基于GTR台面终端结构,在功率M O SFET中引入了一种类似的沟槽负斜角终端结构。利用ISE软件对其耐压机理和击穿特性进行了模拟与分析。结果表明,采用沟槽负斜角终端结构会使功率M O SFET的耐压达到其平行平面结击穿电压的92.6%,而所占的终端尺寸仅为场限环的80%。展开更多
Based on the surface-gate and buried-gate structures,a novel buried-gate structure called the planar type buried-gate (PTBG) structure for static induction devices (SIDs) is proposed.An approach to realize a buried-ga...Based on the surface-gate and buried-gate structures,a novel buried-gate structure called the planar type buried-gate (PTBG) structure for static induction devices (SIDs) is proposed.An approach to realize a buried-gate type static induction transistor by conventional planar process technology is presented.Using this structure,it is successfully avoided the second epitaxy with a high degree of difficulty and the complicated mesa process in conventional buried gate.The experimental results demonstrate that this structure is desirable for application in power SIDs.Its advantages are high breakdown voltage and blocking gain.展开更多
文摘WT8.BZ]A new quasi 2-dimensional analytical approach to predicting the ring voltage,edge peak fields and optimal spacing of the planar junction with a single floating field limiting ring structure has been proposed,based on the cylindrical symmetric solution and the critical field concept.The effects of the spacing and reverse voltage on the ring junction voltage and edge peak field profiles have been analyzed.The optimal spacing and the maximum breakdown voltage of the structure have also been obtained.The analytical results are in excellent agreement with that obtained from the 2-D device simulator,MEDICI and the reported result,which proves the presented model valid.
文摘A vertical sandwich deep trench with a field limiting ring is proposed to improve the breakdown voltage of power devices and high voltage devices.Simulation result shows that nearly 100% breakdown voltage of the plane junction can be realized.
基金supported by the Guangxi Provincial Natural Science Foundation,China(Grant No.2010GXNSFB013054)the Guangxi Provincial Key Science and Technology Program,China(Grant No.11107001-20)
文摘A novel thin drift region device with heavily doped N＋ rings embedded in the substrate is reported, which is called the field limiting rings in substrate lateral double-diffused MOS transistor （SFLR LDMOS）. In the SFLR LDMOS, the peak of the electric field at the main junction is reduced due to the transfer of the voltage from the main junction to other field limiting ring junctions, so the vertical electric field is improved significantly. A model of the breakdown voltage is developed, from which optimal spacing is obtained. The numerical results indicate that the breakdown voltage of the device proposed is increased by 76% in comparison to that of the conventional LDMOS.
基金Project supported by the State Key Program of the National Natural Science Foundation of China(Grant No.61234006)
文摘This paper describes the successful fabrication of 4H-SiC junction barrier Schottky （JBS） rectifiers with a linearly graded field limiting ring （LG-FLR）. Linearly variable ring spacings for the FLR termination are applied to improve the blocking voltage by reducing the peak surface electric field at the edge termination region, which acts like a variable lateral doping profile resulting in a gradual field distribution. The experimental results demonstrate a breakdown voltage of 5 kV at the reverse leakage current density of 2 mA/cm2 （about 80% of the theoretical value）. Detailed numerical simulations show that the proposed termination structure provides a uniform electric field profile compared to the conventional FLR termi- nation, which is responsible for 45% improvement in the reverse blocking voltage despite a 3.7% longer total termination length.
文摘对常用的场限环(FLR)和正、负斜角终端结构的耐压机理进行了简要分析,讨论了其结构参数的优化方法。基于GTR台面终端结构,在功率M O SFET中引入了一种类似的沟槽负斜角终端结构。利用ISE软件对其耐压机理和击穿特性进行了模拟与分析。结果表明,采用沟槽负斜角终端结构会使功率M O SFET的耐压达到其平行平面结击穿电压的92.6%,而所占的终端尺寸仅为场限环的80%。
文摘Based on the surface-gate and buried-gate structures,a novel buried-gate structure called the planar type buried-gate (PTBG) structure for static induction devices (SIDs) is proposed.An approach to realize a buried-gate type static induction transistor by conventional planar process technology is presented.Using this structure,it is successfully avoided the second epitaxy with a high degree of difficulty and the complicated mesa process in conventional buried gate.The experimental results demonstrate that this structure is desirable for application in power SIDs.Its advantages are high breakdown voltage and blocking gain.
