Reverse blocking characteristics and mechanisms in Schottky-drain AlGaN/GaN HEMT with a drain field plate and floating field plates

In this paper, a novel A1GaN/GaN HEMT with a Schottky drain and a compound field plate （SD-CFP HEMT） is presented for the purpose of better reverse blocking capability. The compound field plate （CFP） consists of a drain field plate （DFP） and several floating field plates （FFPs）. The physical mechanisms of the CFP to improve the reverse breakdown voltage and to modulate the distributions of channel electric field and potential are investigated by two-dimensional numer- ical simulations with Silvaco-ATLAS. Compared with the HEMT with a Schottky drain （SD HEMT） and the HEMT with a Schottky drain and a DFP （SD-FP HEMT）, the superiorities of SD-CFP HEMT lie in the continuous improvement of the reverse breakdown voltage by increasing the number of FFPs and in the same fabrication procedure as the SD-FP HEMT. Two useful optimization laws for the SD-CFP HEMTs are found and extracted from simulation results. The relationship between the number of the FFPs and the reverse breakdown voltage as well as the FP efficiency in SD-CFP HEMTs are discussed. The results in this paper demonstrate a great potential of CFP for enhancing the reverse blocking ability in A1GaN/GaN HEMT and may be of great value and significance in the design and actual manufacture of SD-CFP HEMTs.

Improvement of Electrical Performance of SOI-LIGBT by Resistive Field Plate

The electrical performance including breakdown voltage and turn-off speed of SOI-LIGBT is improved by incorporating a resistive field plate (RFP) and a p-MOSFET.The p-MOSFET is controlled by a signal detected from a point of the RFP.During the turning-off of the IGBT,the p-MOSFET is turned on,which provides a channel for the excessive carriers to flow out of the drift region and prevents the carriers from being injected into the drift region.At the same time,the electric field affected by the RFP makes the excessive carriers flow through a wider region,which almost eliminates the second phase of the turning-off of the SOI-LIGBT caused by the substrate bias.Faster turn-off speed is achieved by above two factors.During the on state of the IGBT,the p-MOSFET is off,which leads to an on-state performance like normal one.At least,the increase of the breakdown voltage for 25% and the decrease of the turn-off time for 65% can be achieved by this structure as can be verified by the numerical simulation results.

A low specific on-resistance SOI LDMOS with a novel junction field plate

A low specific on-resistance SO1 LDMOS with a novel junction field plate （JFP） is proposed and investigated theo- retically. The most significant feature of the JFP LDMOS is a PP-N junction field plate instead of a metal field plate. The unique structure not only yields charge compensation between the JFP and the drift region, but also modulates the surface electric field. In addition, a trench gate extends to the buffed oxide layer （BOX） and thus widens the vertical conduction area. As a result, the breakdown voltage （BV） is improved and the specific on-resistance （Ron,sp） is decreased significantly. It is demonstrated that the BV of 306 V and the Ron,sp of 7.43 mΩ.cm2 are obtained for the JFP LDMOS. Compared with those of the conventional LDMOS with the same dimensional parameters, the BV is improved by 34.8%, and the Ron,sp is decreased by 56.6% simultaneously. The proposed JFP LDMOS exhibits significant superiority in terms of the trade-off between BV and Ron,sp. The novel JFP technique offers an alternative technique to achieve high blocking voltage and large current capacity for power devices.

A Lateral Regulator Diode with Field Plates for Light-Emitting-Diode Lighting

A lateral current regulator diode （CRD） with field plates is proposed and experimentally demonstrated. The proposed CFtD is based on the junction field-effect transistor （JFET） structure. A cathode field plate is adopted to alleviate the channel-length modulation effect and to improve the saturated I-V characteristics. An anode field plate is induced to achieve a high breakdown voltage VB of the CRD. The influence of the key device parameters on the I-V characteristics of the lateral CRD are discussed. Experimental results show that the proposed CRD presents good I-V characteristics with a high VB about 180 V and a low knee voltage （Vk） below 3 V. Furthermore, the proposed CRD has a negative temperature coefficient. The well characteristic of the proposed CRD makes it a cost-effective solution for light-emitting-diode lighting.

A simulation study of field plate termination in Ga2O3 Schottky barrier diodes

In this work, the field plate termination is studied for Ga2O3Schottky barrier diodes(SBDs) by simulation. The influence of field plate overlap, dielectric material and thickness on the termination electric field distribution are demonstrated.It is found that the optimal thickness increases with reverse bias increasing for all the three dielectrics of SiO2, Al2O3, and HfO2. As the thickness increases, the maximum electric field intensity decreases in SiO2and Al2O3, but increases in HfO2.Furthermore, it is found that SiO2and HfO2are suitable for the 600 V rate Ga2O3SBD, and Al2O3is suitable for both600 V and 1200 V rate Ga2O3SBD. In addition, the comparison of Ga2O3SBDs between the SiC and GaN counterpart reveals that for Ga2O3, the breakdown voltage bottleneck is the dielectric. While, for SiC and GaN, the bottleneck is mainly the semiconductor itself.

Breakdown voltage model and structure realization of a thin silicon layer with linear variable doping on a silicon on insulator high voltage device with multiple step field plates

Based on the theoretical and experimental investigation of a thin silicon layer（TSL） with linear variable doping（LVD） and further research on the TSL LVD with a multiple step field plate（MSFP）,a breakdown voltage（BV） model is proposed and experimentally verified in this paper.With the two-dimensional Poisson equation of the silicon on insulator（SOI） device,the lateral electric field in drift region of the thin silicon layer is assumed to be constant.For the SOI device with LVD in the thin silicon layer,the dependence of the BV on impurity concentration under the drain is investigated by an enhanced dielectric layer field（ENDIF）,from which the reduced surface field（RESURF） condition is deduced.The drain in the centre of the device has a good self-isolation effect,but the problem of the high voltage interconnection（HVI） line will become serious.The two step field plates including the source field plate and gate field plate can be adopted to shield the HVI adverse effect on the device.Based on this model,the TSL LVD SOI n-channel lateral double-diffused MOSFET（nLDMOS） with MSFP is realized.The experimental breakdown voltage（BV） and specific on-resistance（R on,sp） of the TSL LVD SOI device are 694 V and 21.3 ·mm 2 with a drift region length of 60 μm,buried oxide layer of 3 μm,and silicon layer of 0.15 μm,respectively.

Influence of a drain field plate on the forward blocking characteristics of an AlGaN/GaN high electron mobility transistor

In this paper, the influence of a drain field plate （FP） on the forward blocking characteristics of an AlGaN/GaN high electron mobility transistor （HEMT） is investigated. The HEMT with only a gate FP is optimized, and breakdown voltage VBR is saturated at 1085 V for gate–drain spacing LGD ≥ 8 μm. On the basis of the HEMT with a gate FP, a drain FP is added with LGD=10 μm. For the length of the drain FP LDF ≤ 2 μm, VBR is almost kept at 1085 V, showing no degradation. When LDF exceeds 2 μm, VBR decreases obviously as LDF increases. Moreover, the larger the LDF, the larger the decrease of VBR. It is concluded that the distance between the gate edge and the drain FP edge should be larger than a certain value to prevent the drain FP from affecting the forward blocking voltage and the value should be equal to the LGD at which VBR begins to saturate in the first structure. The electric field and potential distribution are simulated and analyzed to account for the decrease of VBR.

Field plate structural optimization for enhancing the power gain of GaN-based HEMTs

A novel source-connected field plate structure, featuring the same photolithography mask as the gate electrode, is proposed as an improvement over the conventional field plate （FP） techniques to enhance the frequency performance in GaN-based HEMTs. The influences of the field plate on frequency and breakdown performance are investigated simul- taneously by using a two-dimensional physics-based simulation. Compared with the conventional T-gate structures with a field plate length of 1.2 gm, this field plate structure can induce the small signal power gain at 10 GHz to increase by 5-9.5 dB, which depends on the distance between source FP and dramatically shortened gate FE This technique minimizes the parasitic capacitances, especially the gate-to-drain capacitance, showing a substantial potential for millimeter-wave, high power applications.

High-voltage SOI lateral MOSFET with a dual vertical field plate

A new silicon-on-insulator （SOI） power lateral MOSFET with a dual vertical field plate （VFP） in the oxide trench is proposed. The dual VFP modulates the distribution of the electric field in the drift region, which enhances the internal field of the drift region and increases the drift doping concentration of the drift region, resulting in remarkable improvements in breakdown voltage （BV） and specific on-resistance （Ron,sp）. The mechanism of the VFP is analyzed and the characteristics of BV and Ron,sp are discussed. It is shown that the BV of the proposed device increases from 389 V of the conventional device to 589 V, and the Ron,sp decreases from 366 mΩ·cm2 to 110 mΩ·cm2.

Enhancement of off-state characteristics in junctionless field effect transistor using a field plate

In this paper, a novel junctionless field effect transistor（JLFET） is proposed. In the presence of a field plate between gate and drain, the gate-induced drain leakage（GIDL） effect is suppressed due to the decrease of lateral band-to-band tunneling probability. Thus, the off-state current Ioff, which is mainly provided by the GIDL current, is reduced. Sentaurus simulation shows that the Ioffof the new optimized JLFET is reduced by ～ 2 orders and its sub-threshold swing can reach76.8 mV/decade with little influence on its on-state current Ion, so its Ion/Ioff ratio is improved by 2 orders of magnitude compared with that of the normal JLFET. Optimization of device parameters such as Φfps（the work difference between field plate and substrate） and LFP（the length of field plate）, is also discussed in detail.

A novel LDMOS with a junction field plate and a partial N-buried layer

A novel lateral double-diffused metal–oxide semiconductor（LDMOS） with a high breakdown voltage（BV） and low specific on-resistance（Ron.sp） is proposed and investigated by simulation. It features a junction field plate（JFP） over the drift region and a partial N-buried layer（PNB） in the P-substrate. The JFP not only smoothes the surface electric field（E-field）, but also brings in charge compensation between the JFP and the N-drift region, which increases the doping concentration of the N-drift region. The PNB reshapes the equipotential contours, and thus reduces the E-field peak on the drain side and increases that on the source side. Moreover, the PNB extends the depletion width in the substrate by introducing an additional vertical diode, resulting in a significant improvement on the vertical BV. Compared with the conventional LDMOS with the same dimensional parameters, the novel LDMOS has an increase in BV value by 67.4%,and a reduction in Ron.sp by 45.7% simultaneously.

4H-SiC Schottky barrier diodes with semi-insulating polycrystalline silicon field plate termination

Based on the theoretical analysis of the 4H-SiC Schottky-barrier diodes （SBDs） with field plate termination, 4H-SiC SBD with semi-insulating polycrystalline silicon （SIPOS） FP termination has been fabricated. The relative dielectric con-stant of the SIPOS dielectric first used in 4H-SiC devices is 10.4, which is much higher than that of the SiO2 dielectric, leading to benefitting the performance of devices. The breakdown voltage of the fabricated SBD could reach 1200 V at leak-age current 20 μA, about 70% of the theoretical breakdown voltage. Meanwhile, both of the simulation and experimental results show that the length of the SIPOS FP termination is an important factor for structure design.

Theoretical analysis for AlGaN avalanche photodiodes with mesa and field plate structure

To suppress the electric field crowding at sidewall and improve the detection sensitivity of the AlGaN separate absorption and multiplication(SAM)avalanche photodiodes(APDs),we propose the new AlGaN APDs structure combining a large-area mesa with a field plate(FP).The simulated results show that the proposed AlGaN APDs exhibit a significant increase in avalanche gain,about two orders of magnitude,compared to their counterparts without FP structure,which is attributed to the suppression of electric field crowding at sidewall of multiplication layer and the reduction of the maximum electric field at the p-type GaN sidewall in p-n depletion region.Meanwhile,the APDs can produce an obviously enhanced photocurrent due to the increase in cross sectional area of multiplication region.

Reverse blocking enhancement of drain field plate in Schottky-drain AlGaN/GaN high-electron mobility transistors

In this paper, we present the combination of drain field plate （FP） and Schottky drain to improve the reverse blocking capability, and investigate the reverse blocking enhancement of drain FP in Schottky-drain AlGaN/GaN high-electron mobility transistors （HEMTs）. Drain FP and gate FP were employed in a two-dimensional simulation to improve the reverse blocking voltage （VRB） and the forward blocking voltage （VFB）. The drain-FP length, the gate-FP length and the passivation layer thickness were optimized. VRB and VFB were improved from -67 V and 134 V to -653 V and 868 V respectively after optimization. Simulation results suggest that the combination of drain FP and Schottky drain can enhance the reverse blocking capability significantly.

Influence of field plate on surface-state-related lag characteristics of AlGaN/GaN HEMT

The relationship between A1GaN/GaN HEMT gate field plate （FP） and surface-state-related gate lag phenomena is investigated by two-dimensional numerical transient simulations to study the mechanism of the influence of FPs on current collapse. The simulations reveal that adding a field plate has a noticeable impact on the extent of current collapse while it has no influence on lapsed time. The FP is found to suppress current collapse through reducing the ionization probability of surface states by enhancing free hole accumulation next to the AIGaN surface between gate and drain.

Field plated 0.15μm GaN HEMTs for millimeter-wave application

SiN dielectrically-defined 0.15μm field plated GaN HEMTs for millimeter-wave application have been presented.The AlGaN/GaN hetero-structure epitaxial material for HEMTs fabrication was grown on a 3-inch SiC substrate with an Fe doped GaN buffer layer by metal-organic chemical deposition.Electron beam lithography was used to define both the gate footprint and the cap of the gate with an integrated field plate.Gate recessing was performed to control the threshold voltage of the devices.The fabricated GaN HEMTs exhibited a unit current gain cut-off frequency of 39 GHz and a maximum frequency of oscillation of 63 GHz.Load-pull measurements carried out at 35 GHz showed a power density of 4 W/mm with associated power gain and power added efficiency of 5.3 dB and 35%,respectively,for a 0.15 mm gate width device operated at a 24 V drain bias.The developed 0.15μm gate length GaN HEMT technology is suitable for Ka band applications and is ready for millimeter-wave power MMICs development.

Ultralow specific ON-resistance high-k LDMOS with vertical field plate

An ultralow specific on-resistance high-k LDMOS with vertical field plate（VFP HK LDMOS） is proposed. The high-k dielectric trench and highly doped interface N＋ layer are made in bulk silicon to reduce the surface field of the drift region in the VFP HK LDMOS. The gate vertical field plate（VFP） pinning in the high-k dielectric trench can modulate the bulk electric field. The high-k dielectric not only provides polarized charges to assist depletion of the drift region, so that the drift region and high-k trench maintain charge balance adaptively,but also can fully assist in depleting the drift region to increase the drift doping concentration and reshape the electric field to avoid premature breakdown. Compared with the conventional structure, the VFP HK LDMOS has the breakdown voltage of 629.1 V at the drift length of 40 μm and the specific on-resistance of 38.4 mΩ·cm^2 at the gate potential of 15 V. Then the power figure of merit is 10.31 MW/cm^2.

4H-SiC trench gate MOSFETs with field plate termination

Field plate(FP)-terminated 4H-SiC trench gate MOSFETs are demonstrated in this work.N+/P?/N?/N+multiple epitaxial layers were grown on 3-inch N+type 4H-SiC substrate by chemical vapor deposition(CVD),and then the 4H-SiC trench gate MOSFETs were fabricated based on the standard trench transistor fabrication.Current-voltage measurements in forward and reverse bias have been performed on different devices with and without FP protections.It is found that more than 60%of the devices protected with FP termination are able to block 850 V.The measurements also show that the devices have the small leakage currents 0.15 nA at 600 V and 2.5 nA at 800 V,respectively.The experimental results also were compared with the simulated results,which show good agreement with each other in the trend.The limited performance of the devices is mainly because of the damage induced on the trench sidewalls from the etching process and the quality of the SiO2 films.Therefore,the 4H-SiC trench gate MOSFETs are expected to be optimized by reducing the etching damage and growing high-quality SiO2 dielectric films.

Field plate engineering for GaN-based Schottky barrier diodes

The practical design of GaN-based Schottky barrier diodes （SBDs） incorporating a field plate （FP） structure necessitates an understanding of their working mechanism and optimization criteria. In this work, the influences of the parameters of FPs upon breakdown of the diode are investigated in detail and the design rules of FP structures for GaN-based SBDs are presented for a wide scale of material and device parameters. By comparing three representative dielectric materials （SiO2, Si3N4 and Al2O3） selected for fabricating FPs, it is found that the product of dielectric permittivity and critical field strength of a dielectric material could be used as an index to predict its potential performance for FP applications.

A 680 V LDMOS on a thin SOI with an improved field oxide structure and dual field plate

A 680 V LDMOS on a thin SOI with an improved field oxide（FOX） and dual field plate was studied experimentally.The FOX structure was formed by an ＂oxidation-etch-oxidation＂ process,which took much less time to form,and had a low protrusion profile.A polysilicon field plate extended to the FOX and a long metal field plate was used to improve the specific on-resistance.An optimized drift region implant for linear-gradient doping was adopted to achieve a uniform lateral electric field.Using a SimBond SOI wafer with a 1.5μm top silicon and a 3μm buried oxide layer,CMOS compatible SOI LDMOS processes are designed and implemented successfully. The off-state breakdown voltage reached 680 V,and the specific on-resistance was 8.2Ω·mm^2.