Topological horseshoe analysis and field-programmable gate array implementation of a fractional-order four-wing chaotic attractor

We present a fractional-order three-dimensional chaotic system, which can generate four-wing chaotic attractor. Dynamics of the fractional-order system is investigated by numerical simulations. To rigorously verify the chaos properties of this system, the existence of horseshoe in the four-wing attractor is presented. Firstly, a Poincare′ section is selected properly, and a first-return Poincare′ map is established. Then, a one-dimensional tensile horseshoe is discovered, which verifies the chaos existence of the system in mathematical view. Finally, the fractional-order chaotic attractor is implemented physically with a field-programmable gate array(FPGA) chip, which is useful in further engineering applications of information encryption and secure communications.

Resonance Characteristics of Piezoelectric Resonator Based on Digital Driving Circuit of Field-Programmable Gate Array

Piezoelectric resonators are widely used in frequency reference devices, mass sensors, resonant sensors(such as gyros and accelerometers), etc. Piezoelectric resonators usually work in a special resonant mode. Obtaining working resonant mode with high quality is key to improve the performance of piezoelectric resonators. In this paper, the resonance characteristics of a rectangular lead zirconium titanate(PZT) piezoelectric resonator are studied. On the basis of the field-programmable gate array(FPGA) embedded system, direct digital synthesizer(DDS) and automatic gain controller(AGC) are used to generate the driving signals with precisely adjustable frequency and amplitude. The driving signals are used to excite the piezoelectric resonator to the working vibration mode. The influence of the connection of driving electrodes and voltage amplitude on the vibration of the resonator is studied. The quality factor and vibration linearity of the resonator are studied with various driving methods mentioned in this paper. The resonator reaches resonant mode at 330 kHz by different driving methods.The relationship between resonant amplitude and driving signal amplitude is linear. The quality factor reaches over 150 by different driving methods. The results provide a theoretical reference for the efficient excitation of the piezoelectric resonator.

SIES:A Novel Implementation of Spiking Convolutional Neural Network Inference Engine on Field-Programmable Gate Array

Neuromorphic computing is considered to be the future of machine learning,and it provides a new way of cognitive computing.Inspired by the excellent performance of spiking neural networks(SNNs)on the fields of low-power consumption and parallel computing,many groups tried to simulate the SNN with the hardware platform.However,the efficiency of training SNNs with neuromorphic algorithms is not ideal enough.Facing this,Michael et al.proposed a method which can solve the problem with the help of DNN(deep neural network).With this method,we can easily convert a well-trained DNN into an SCNN(spiking convolutional neural network).So far,there is a little of work focusing on the hardware accelerating of SCNN.The motivation of this paper is to design an SNN processor to accelerate SNN inference for SNNs obtained by this DNN-to-SNN method.We propose SIES(Spiking Neural Network Inference Engine for SCNN Accelerating).It uses a systolic array to accomplish the task of membrane potential increments computation.It integrates an optional hardware module of max-pooling to reduce additional data moving between the host and the SIES.We also design a hardware data setup mechanism for the convolutional layer on the SIES with which we can minimize the time of input spikes preparing.We implement the SIES on FPGA XCVU440.The number of neurons it supports is up to 4000 while the synapses are 256000.The SIES can run with the working frequency of 200 MHz,and its peak performance is 1.5625 TOPS.

A Two-Stage Method for Routing in Field-Programmable Gate Arrays with Time-Division Multiplexing

Emerging applications widely use field-programmable gate array(FPGA)prototypes as a tool to verify modern very-large-scale integration(VLSI)circuits,imposing many problems,including routing failure caused by the limited number of connections among blocks of FPGAs therein.Such a shortage of connections can be alleviated through time-division multiplexing(TDM),by which multiple signals sharing an identical routing channel can be transmitted.In this context,the routing quality dominantly decides the performance of such systems,proposing the requirement of minimizing the signal delay between FPGA pairs.This paper proposes algorithms for the routing problem in a multi-FPGA system with TDM support,aiming to minimize the maximum TDM ratio.The algorithm consists of two major stages:(1)A method is proposed to set the weight of an edge according to how many times it is shared by the routing requirements and consequently to compute a set of approximate minimum Steiner trees.(2)A ratio assignment method based on the edge-demand framework is devised for assigning ratios to the edges respecting the TDM ratio constraints.Experiments were conducted against the public benchmarks to evaluate our proposed approach as compared with all published works,and the results manifest that our method achieves a better TDM ratio in comparison.

Design and development of multi-channel front end electronics based on dual-polarity charge-to-digital converter for SiPM detector applications

With the development of silicon photomultiplier(SiPM)technology,front-end electronics for SiPM signal processing have been highly sought after in various fields.A compact 64-channel front-end electronics(FEE)system achieved by fieldprogrammable gate array-based charge-to-digital converter(FPGA-QDC)technology was built and developed.The FEE consists of an analog board and FPGA board.The analog board incorporates commercial amplifiers,resistors,and capacitors.The FPGA board is composed of a low-cost FPGA.The electronics performance of the FEE was evaluated in terms of noise,linearity,and uniformity.A positron emission tomography(PET)detector with three different readout configurations was designed to validate the readout capability of the FEE for SiPM-based detectors.The PET detector was made of a 15×15 lutetium–yttrium oxyorthosilicate(LYSO)crystal array directly coupled with a SiPM array detector.The experimental results show that FEE can process dual-polarity charge signals from the SiPM detectors.In addition,it shows a good energy resolution for 511-keV gamma photons under the dual-end readout for the LYSO crystal array irradiated by a Na-22 source.Overall,the FEE based on FPGA-QDC shows promise for application in SiPM-based radiation detectors.

FPGA-based acceleration for binary neural networks in edge computing

As a core component in intelligent edge computing,deep neural networks(DNNs)will increasingly play a critically important role in addressing the intelligence-related issues in the industry domain,like smart factories and autonomous driving.Due to the requirement for a large amount of storage space and computing resources,DNNs are unfavorable for resource-constrained edge computing devices,especially for mobile terminals with scarce energy supply.Binarization of DNN has become a promising technology to achieve a high performance with low resource consumption in edge computing.Field-programmable gate array(FPGA)-based acceleration can further improve the computation efficiency to several times higher compared with the central processing unit(CPU)and graphics processing unit(GPU).This paper gives a brief overview of binary neural networks(BNNs)and the corresponding hardware accelerator designs on edge computing environments,and analyzes some significant studies in detail.The performances of some methods are evaluated through the experiment results,and the latest binarization technologies and hardware acceleration methods are tracked.We first give the background of designing BNNs and present the typical types of BNNs.The FPGA implementation technologies of BNNs are then reviewed.Detailed comparison with experimental evaluation on typical BNNs and their FPGA implementation is further conducted.Finally,certain interesting directions are also illustrated as future work.

主被动均衡电池管理系统设计

为了克服新能源汽车电池组在使用过程中内部单体电池充放电速率不一致问题,提出了一种基于现场可编程门阵列(field-programmable gate array,FPGA)的主被动均衡相结合的电池管理系统。该设计通过LTC6811电池采集芯片,将电压、电流、温度等数据传到FPGA进行容量估算。主控微控制单元(microcontroller unit,MCU)通过设置单体间荷电状态(state of charge,SOC)差值阈值,控制均衡电路中的回路开关的通断,使单体电池在不同容量差值时,进行不同的均衡策略。同时运用MATLAB/Simulink仿真软件搭建出核心主被动均衡电路模型,对电路的均衡方案进行仿真分析。仿真结果表明:通过采用主被动相结合的均衡策略,电池在充放电过程中均衡速度较单一均衡方式有明显的提升。可见通过主被动均衡结合的方式,能有效地提升电池均衡速度,改善电池使用效率。

BD2/GPS高精度同步时钟装置的设计与应用

针对CCD(Charge Coupled Device)相机在探测脉冲激光光斑过程中曝光时刻与脉冲激光同步的问题,提出一种利用超前预测方式同步触发CCD相机抓拍光斑图像的高精度时钟源设计方案。该装置主要采用北斗2导航系统(BD2:BeiDou2 navigation satellite system)/全球定位系统(GPS:Global Positioning System),双模接收单元提供的协调世界时(UTC:Universal Time Coordinated)时间以及高精度秒脉冲(PPS:One-Pulse Per Second)时间基准作为同步时钟装置的基准源,并结合现场可编程门阵列(FPGA:Field-Programmable Gate Array)高速时序计算与微控制单元接口技术,保证CCD相机同步抓拍时间,从而完成高精度的同步触发。实验表明,该装置可以提供微秒级时间同步精度和标准授时信息,有效地缩短了CCD相机曝光时间,得到完整清晰的高信噪比脉冲激光光斑图像。

基于机器视觉的坯布疵点实时自动检测平台

为了克服人工检测坯布疵点过程中存在的低效率、高误检率、高漏检率等问题,设计并实现了一款能兼顾实时性和准确性要求的坯布自动检测平台.该平台包括织物传动系统、光源和成像系统、图像采集与处理系统、人机交互系统4个组成部分.在详细阐述了图像采集与处理系统的设计之后,结合AR谱算法对坯布自动检测平台进行了相关调试和试验验证,结果表明该平台已实现了预期的研发要求.

便携式可在线编程雷达信号模拟器

随着雷达接收机系统的日益复杂,雷达信号模拟器日益成为现场测试中的必备工具.根据测试雷达的型号不同,或调试、测试的内容不同,对雷达信号模拟器提供的模拟信号也有着完全不同的要求.为了满足现场测试中,对具备多种信号输出能力的信号模拟器的需求,本文研究设计了一套可在线编程的便携式雷达信号模拟器.该模拟器可以按照测试需求,输出典型的杂波、目标和噪声调制信号,也可以通过universal serial bus(USB)接口与personal computer(PC)机相连,通过实时在线编程,产生测试所需的信号,提高了雷达信号模拟器的实用范围,同时也提升了雷达信号模拟器的便携性.本系统通过计算机软件系统生成雷达信号仿真数据,通过USB总线交互模块实现数据在模拟器和计算机系统之间的交互,运用field-programmable gate array(FPGA)控制模块控制数据的下载,存储和输出,利用Flash实现离电信号储存,采用四片高速RAM进行信号实时输出.本文全面阐述了雷达信号模拟系统的工作原理,介绍了该系统设计方案,着重阐述了模块间的硬件接口及控制模块.该系统体积小,便于携带,改变模拟信号类型方便,具有较好的灵活性和通用性.

基于FPGA的千兆以太网协议分析技术

该文主要阐述在FPGA(Field-Programmable Gate Array)内千兆以太网协议数据流帧的生成、编码、组帧、解帧及协议帧分析,详细地阐述了BCM5421和FPGA组合的硬件设计技术、协议发生的FPGA设计技术、协议解码、过滤、性能分析的FPGA设计技术等关键技术的实现途径。

Online volume rendering of incrementally accumulated LSCEM images for superficial oral cancer detection

Laser scanning confocal endomicroscope(LSCEM)has emerged as an imaging modality which provides noninvasive,in vivo imaging of biological tissue on a microscopic scale.Scientific visualizations for LSCEM datasets captured by current imaging systems require these datasets to be fully acquired and brought to a separate rendering machine.To extend the features and capabilities of this modality,we propose a system which is capable of performing realtime visualization of LSCEM datasets.Using field-programmable gate arrays,our system performs three tasks in parallel:(1)automated control of dataset acquisition;(2)imaging-rendering system synchronization;and(3)realtime volume rendering of dynamic datasets.Through fusion of LSCEM imaging and volume rendering processes,acquired datasets can be visualized in realtime to provide an immediate perception of the image quality and biological conditions of the subject,further assisting in realtime cancer diagnosis.Subsequently,the imaging procedure can be improved for more accurate diagnosis and reduce the need for repeating the process due to unsatisfactory datasets.

Study on GNSS satellite signal simulator

Satellite signal simulator for global navigation satellite system(GNSS)can evaluate the accuracy of capturing,tracing and positioning of GNSS receiver.It has significant use-value in the military and civil fields.The system adopts the overall design scheme of digital signal processor(DSP)and field-programmable gate array(FPGA).It consists of four modules:industrial control computer simulation software,mid-frequency signal generator,digital-to-analog(D/A)module and radio frequency(RF)module.In this paper,we test the dynamic performance of simulator using the dynamic scenes testing method,and the signal generated by the designed simulator is primarily validated.

ARCHITECTURE MODEL AND RESOURCE GRAPH BUILDING ALGORITHM FOR DETAILED FPGA ARCHITECTURE DESIGN

This paper addresses the issue of designing the detailed architectures of Field-Programmable Gate Arrays(FPGAs), which has a great impact on the overall performances of an FPGA in practice. Firstly, a novel FPGA architecture description model is proposed based on an easy-to-use file format known as YAML. This format permits the description of any detailed architecture of hard blocks and channels. Then a general algorithm of building FPGA resource graph is presented. The proposed model is scalable and capable of dealing with detailed architecture design and can be used in FPGA architecture evaluation system which is developed to enable detailed architecture design. Experimental results show that a maximum of 16.36% reduction in total wirelength and a maximum of 9.34% reduction in router effort can be obtained by making very little changes to detailed architectures, which verifies the necessity and effectiveness of the proposed model.

FPGA implementation of fractal patterns classifier for multiple cardiac arrhythmias detection

This paper proposes the fractal patterns classifier for multiple cardiac arrhythmias on field-programmable gate array (FPGA) device. Fractal dimension transformation (FDT) is employed to adjoin the fractal features of QRS-complex, including the supraventricular ectopic beat, bundle branch ectopic beat, and ventricular ectopic beat. FDT with fractal dimension (FD) is addressed for constructing various symptomatic patterns, which can produce family functions and enhance features, making clear differences between normal and unhealthy subjects. The probabilistic neural network (PNN) is proposed for recognizing multiple cardiac arrhythmias. Numerical experiments verify the efficiency and higher accuracy with the software simulation in order to formulate the mathematical model logical circuits. FDT results in data self-similarity for the same arrhythmia category, the number of dataset requirement and PNN architecture can be reduced. Its simplified model can be easily embedded in the FPGA chip. The prototype classifier is tested using the MIT-BIH arrhythmia database, and the tests reveal its practicality for monitoring ECG signals.

High performance hardware architecture for depth measurement by using binocular-camera

High performance hardware architecture for depth measurement by using binocular-camera is proposed.In the system,at first,video streams of the target are captured by left and right charge-coupled device(CCD)cameras to obtain an image including the target.Then,two different images with two different view points are obtained,and they are used in calculating the position deviation of the image's pixels based on triangular measurement.Finally,the three-dimensional coordinate of the object is reconstructed.All the video data is processed by using field-programmable gate array(FPGA)in real-time.Hardware implementation speeds up the performance and reduces the power,thus,this hardware architecture can be applied in the portable environment.

Erosion thermocouple temperature acquisition system

Aiming at high requirements of temperature measurement system in high temperature,high pressure,highly corrosive and other special environments,a temperature acquisition system based on field-programmable gate array(FPGA) which is the controller of the system is designed.Also a Flash memory is used as the memory and an erosion thermocouple is used as sensor of the system.Compared with the traditional system using complex programmable logic device(CPLD)and microcontroller unit(MCU)as the main body,this system has some advantages,such as short response time,small volume,no loss of data once power is off,high precision,stability and reliability.And the sensor of the system can be reused.In this paper,boiling water experiment is used to verify accuracy of the system.The millisecond level signal from firecrackers is for verifying the stability and fast response characteristics of the system.The results of experiment indicate that the temperature measurement system is more suitable for the field of explosion and other environments which have high requirements for the system.

Design and implementation of high speed TDI CCD timing-driven circuits

The time delay integration charge coupled device(TDI CCD)is the key component in remote sensing systems.The paper analyzes the structure and the working principles of the device according to a customized TDI CCD chip.Employing the special clock resources and large-scale phase locked logic(PLL)in field-programmable gate arrays(FPGA),a timing-driven approach is proposed,using which all timing signals including reset gate,horizontal and vertical timing signals,are implemented in one chip.This not only reduces printed circuit board(PCB)space,but also enhances the portability of the system.By studying and calculating CCD parameters thoroughly,load capacity and power consumption,package,etc,are compared between various candidates chips,and detailed comparison results are also listed in table.Experimental results show that clock generator and driving circuit satisfy the requirements of high speed TDI CCD.

AN INFORMATION FUSION METHOD FOR SENSOR DATA RECTIFICATION

In the applications of water regime monitoring, incompleteness, and inaccuracy of sensor data may directly affect the reliability of acquired monitoring information. Based on the spatial and temporal correlation of water regime monitoring information, this paper addresses this issue and proposes an information fusion method to implement data rectification. An improved Back Propagation (BP) neural network is used to perform data fusion on the hardware platform of a stantion unit, which takes Field-Programmable Gate Array (FPGA) as the core component. In order to verify the effectiveness, five measurements including water level, discharge and velocity are selected from three different points in a water regime monitoring station. The simulation results show that this method can recitify random errors as well as gross errors significantly.

Wake-Up-Word Feature Extraction on FPGA

Wake-Up-Word Speech Recognition task (WUW-SR) is a computationally very demand, particularly the stage of feature extraction which is decoded with corresponding Hidden Markov Models (HMMs) in the back-end stage of the WUW-SR. The state of the art WUW-SR system is based on three different sets of features: Mel-Frequency Cepstral Coefficients (MFCC), Linear Predictive Coding Coefficients (LPC), and Enhanced Mel-Frequency Cepstral Coefficients (ENH_MFCC). In (front-end of Wake-Up-Word Speech Recognition System Design on FPGA) [1], we presented an experimental FPGA design and implementation of a novel architecture of a real-time spectrogram extraction processor that generates MFCC, LPC, and ENH_MFCC spectrograms simultaneously. In this paper, the details of converting the three sets of spectrograms 1) Mel-Frequency Cepstral Coefficients (MFCC), 2) Linear Predictive Coding Coefficients (LPC), and 3) Enhanced Mel-Frequency Cepstral Coefficients (ENH_MFCC) to their equivalent features are presented. In the WUW- SR system, the recognizer’s frontend is located at the terminal which is typically connected over a data network to remote back-end recognition (e.g., server). The WUW-SR is shown in Figure 1. The three sets of speech features are extracted at the front-end. These extracted features are then compressed and transmitted to the server via a dedicated channel, where subsequently they are decoded.