The development of various artificial electronics and machines would explosively increase the amount of information and data,which need to be processed via in-situ remediation.Bioinspired synapse devices can store and...The development of various artificial electronics and machines would explosively increase the amount of information and data,which need to be processed via in-situ remediation.Bioinspired synapse devices can store and process signals in a parallel way,thus improving fault tolerance and decreasing the power consumption of artificial systems.The organic field effect transistor(OFET)is a promising component for bioinspired neuromorphic systems because it is suitable for large-scale integrated circuits and flexible devices.In this review,the organic semiconductor materials,structures and fabrication,and different artificial sensory perception systems functions based on neuromorphic OFET devices are summarized.Subsequently,a summary and challenges of neuromorphic OFET devices are provided.This review presents a detailed introduction to the recent progress of neuromorphic OFET devices from semiconductor materials to perception systems,which would serve as a reference for the development of neuromorphic systems in future bioinspired electronics.展开更多
The multi-gate transistors such as Fin-FETs, Tri-gate FETs, and Gate-all-around （GAA） FETs are remarkable breakthrough in the electronic industry. 3D Transistor is taking the place of the conventional 2D planar tran...The multi-gate transistors such as Fin-FETs, Tri-gate FETs, and Gate-all-around （GAA） FETs are remarkable breakthrough in the electronic industry. 3D Transistor is taking the place of the conventional 2D planar transistor for many reasons. 3D transistors afford more scalability, energy efficient performance than planar transistors and increase the control on the channel region to reduce the short channel effect, which enables us to extend Moore＇s law to further extent. In this paper, we will present a review about their structure, operation, types and fabrication.展开更多
The fabrication and characterization of 1700 V 7 A 4H-SiC vertical double-implanted metal-oxide-semiconductor field-effect transistors （VDMOSFETs） are reported. The drift layer is 17μm in thickness with 5 × 10...The fabrication and characterization of 1700 V 7 A 4H-SiC vertical double-implanted metal-oxide-semiconductor field-effect transistors （VDMOSFETs） are reported. The drift layer is 17μm in thickness with 5 × 10^15 cm^-3 n-type doping, and the channel length is 1μm. The MOSFETs show a peak mobility of 17cm2/V.s and a typical threshold voltage of 3 V. The active area of 0.028cm2 delivers a forward drain current of 7A at Vcs = 22 V and VDS= 15 V. The specific on-resistance （Ron,sv） is 18mΩ.cm2 at VGS= 22 V and the blocking voltage is 1975 V （IDS 〈 lOOnA） at VGS = 0 V.展开更多
A single electron transistor based on a silicon-on-insulator is successfully fabricated with electron-beam nano- lithography, inductively coupled plasma etching, thermal oxidation and other techniques. The unique desi...A single electron transistor based on a silicon-on-insulator is successfully fabricated with electron-beam nano- lithography, inductively coupled plasma etching, thermal oxidation and other techniques. The unique design of the pattern inversion is used, and the pattern is transferred to be negative in the electron-beam lithography step. The oxidation process is used to form the silicon oxide tunneling barriers, and to further reduce the effective size of the quantum dot. Combinations of these methods offer advantages of good size controllability and accuracy, high reproducibility, low cost, large-area contacts, allowing batch fabrication of single electron transistors and good integration with a radio-frequency tank circuit. The fabricated single electron transistor with a quantum dot about 50nto in diameter is demonstrated to operate at temperatures up to 70K. The charging energy of the Coulomb island is about 12.5meV.展开更多
Nearly lattice-matched InAIGaN/GaN heterostructure is grown on sapphire substrates by pulsed metal organic chemical vapor deposition and excellent high electron mobility transistors are fabricated on this heterostruct...Nearly lattice-matched InAIGaN/GaN heterostructure is grown on sapphire substrates by pulsed metal organic chemical vapor deposition and excellent high electron mobility transistors are fabricated on this heterostructure. The electron mobility is 1668.08cm2/V.s together with a high two-dimensional-electron-gas density of 1.43 × 10^13 cm-2 for the InAlCaN/CaN heterostructure of 2Onto InAlCaN quaternary barrier. High electron mobility transistors with gate dimensions of 1 × 50 μm2 and 4μm source-drain distance exhibit the maximum drain current of 763.91 mA/mm, the maximum extrinsic transconductance of 163.13 mS/mm, and current gain and maximum oscillation cutoff frequencies of 11 GHz and 21 GHz, respectively.展开更多
A gate-all-around cylindrical （GAAC） transistor for sub-10nm scaling is proposed. The GAAC transistor device physics,TCAD simulation,and proposed fabrication procedure are reported for the first time. Among all othe...A gate-all-around cylindrical （GAAC） transistor for sub-10nm scaling is proposed. The GAAC transistor device physics,TCAD simulation,and proposed fabrication procedure are reported for the first time. Among all other novel FinFET devices, the gate-all-around cylindrical device can be particularly applied for reducing the problems of the conventional multi-gate FinFET and improving the device performance and the scale down capability. According to our simulation,the gate-all-around cylindrical device shows many benefits over conventional multi-gate FinFET, including gate-all- around rectangular （GAAR） devices. With gate-all-around cylindrical architecture,the transistor is controlled by an essen- tially infinite number of gates surrounding the entire cylinder-shaped channel. The electrical integrity within the channel is improved by reducing the leakage current due to the non-symmetrical field accumulation such as the corner effect. The proposed fabrication procedures for devices having GAAC device architecture are also discussed. The method is characterized by its simplicity and full compatibility with conventional planar CMOS technology.展开更多
A simple process flow method for the fabrication of poly-Si nanowire thin film transistors（NW-TFTs） without advanced lithographic tools is introduced in this paper.The cross section of the nanowire channel was manip...A simple process flow method for the fabrication of poly-Si nanowire thin film transistors（NW-TFTs） without advanced lithographic tools is introduced in this paper.The cross section of the nanowire channel was manipulated to have a parallelogram shape by combining a two-step etching process and a spacer formation technique.The electrical and temperature characteristics of the developed NW-TFTs are measured in detail and compared with those of conventional planar TFTs（used as a control）.The as-demonstrated NW-TFT exhibits a small subthreshold swing（191 mV/dec）,a high ON/OFF ratio（8.5 × 10~7）,alow threshold voltage（1.12 V）,a decreased OFF-state current,and a low drain-induced-barrier lowering value（70.11 mV/V）.The effective trap densities both at the interface and grain boundaries are also significantly reduced in the NW-TFT.The results show that all improvements of the NW-TFT originate from the enhanced gate controllability of the multi-gate over the channel.展开更多
增强型氮化镓(GaN)基高电子迁移率晶体管(high electron mobility transistor,HEMT)是高频高功率器件与开关器件领域的研究热点,P-GaN栅技术因具备制备工艺简单、可控且工艺重复性好等优势而成为目前最常用且唯一实现商用的GaN基增强型...增强型氮化镓(GaN)基高电子迁移率晶体管(high electron mobility transistor,HEMT)是高频高功率器件与开关器件领域的研究热点,P-GaN栅技术因具备制备工艺简单、可控且工艺重复性好等优势而成为目前最常用且唯一实现商用的GaN基增强型器件制备方法。首先,概述了当前制约P-GaN栅结构GaN基HEMT器件发展的首要问题,从器件结构与器件制备工艺这2个角度,综述了其性能优化举措方面的最新研究进展。然后,通过对研究进展的分析,总结了当前研究工作面临的挑战以及解决方法。最后,对未来的发展前景、发展方向进行了展望。展开更多
基金the National Natural Science Foundation of China(U21A20497)Singapore National Research Foundation Investigatorship(Grant No.NRF-NRFI08-2022-0009)。
文摘The development of various artificial electronics and machines would explosively increase the amount of information and data,which need to be processed via in-situ remediation.Bioinspired synapse devices can store and process signals in a parallel way,thus improving fault tolerance and decreasing the power consumption of artificial systems.The organic field effect transistor(OFET)is a promising component for bioinspired neuromorphic systems because it is suitable for large-scale integrated circuits and flexible devices.In this review,the organic semiconductor materials,structures and fabrication,and different artificial sensory perception systems functions based on neuromorphic OFET devices are summarized.Subsequently,a summary and challenges of neuromorphic OFET devices are provided.This review presents a detailed introduction to the recent progress of neuromorphic OFET devices from semiconductor materials to perception systems,which would serve as a reference for the development of neuromorphic systems in future bioinspired electronics.
文摘The multi-gate transistors such as Fin-FETs, Tri-gate FETs, and Gate-all-around （GAA） FETs are remarkable breakthrough in the electronic industry. 3D Transistor is taking the place of the conventional 2D planar transistor for many reasons. 3D transistors afford more scalability, energy efficient performance than planar transistors and increase the control on the channel region to reduce the short channel effect, which enables us to extend Moore＇s law to further extent. In this paper, we will present a review about their structure, operation, types and fabrication.
基金Supported by the National Science and Technology Major Project of the Ministry of Science and Technology of China under Grant No 2013ZX02305
文摘The fabrication and characterization of 1700 V 7 A 4H-SiC vertical double-implanted metal-oxide-semiconductor field-effect transistors （VDMOSFETs） are reported. The drift layer is 17μm in thickness with 5 × 10^15 cm^-3 n-type doping, and the channel length is 1μm. The MOSFETs show a peak mobility of 17cm2/V.s and a typical threshold voltage of 3 V. The active area of 0.028cm2 delivers a forward drain current of 7A at Vcs = 22 V and VDS= 15 V. The specific on-resistance （Ron,sv） is 18mΩ.cm2 at VGS= 22 V and the blocking voltage is 1975 V （IDS 〈 lOOnA） at VGS = 0 V.
基金Supported by the National Natural Science Foundation of China under Grant Nos 11074280 and 11403084the Instrument Developing Project of Chinese Academy of Sciences under Grant No YZ201152+2 种基金the Fundamental Research Funds for Central Universities under Grant Nos JUSRP51323B and JUDCF12032the Joint Innovation Project of Jiangsu Province under Grant No BY2013015-19the Graduate Student Innovation Program for Universities of Jiangsu Province under Grant No CXLX12_0724
文摘A single electron transistor based on a silicon-on-insulator is successfully fabricated with electron-beam nano- lithography, inductively coupled plasma etching, thermal oxidation and other techniques. The unique design of the pattern inversion is used, and the pattern is transferred to be negative in the electron-beam lithography step. The oxidation process is used to form the silicon oxide tunneling barriers, and to further reduce the effective size of the quantum dot. Combinations of these methods offer advantages of good size controllability and accuracy, high reproducibility, low cost, large-area contacts, allowing batch fabrication of single electron transistors and good integration with a radio-frequency tank circuit. The fabricated single electron transistor with a quantum dot about 50nto in diameter is demonstrated to operate at temperatures up to 70K. The charging energy of the Coulomb island is about 12.5meV.
基金Supported by the National Science and Technology Major Project of China under Grant No 2013ZX02308-002the National Natural Sciences Foundation of China under Grant Nos 61574108,61334002,61474086 and 61306017
文摘Nearly lattice-matched InAIGaN/GaN heterostructure is grown on sapphire substrates by pulsed metal organic chemical vapor deposition and excellent high electron mobility transistors are fabricated on this heterostructure. The electron mobility is 1668.08cm2/V.s together with a high two-dimensional-electron-gas density of 1.43 × 10^13 cm-2 for the InAlCaN/CaN heterostructure of 2Onto InAlCaN quaternary barrier. High electron mobility transistors with gate dimensions of 1 × 50 μm2 and 4μm source-drain distance exhibit the maximum drain current of 763.91 mA/mm, the maximum extrinsic transconductance of 163.13 mS/mm, and current gain and maximum oscillation cutoff frequencies of 11 GHz and 21 GHz, respectively.
文摘A gate-all-around cylindrical （GAAC） transistor for sub-10nm scaling is proposed. The GAAC transistor device physics,TCAD simulation,and proposed fabrication procedure are reported for the first time. Among all other novel FinFET devices, the gate-all-around cylindrical device can be particularly applied for reducing the problems of the conventional multi-gate FinFET and improving the device performance and the scale down capability. According to our simulation,the gate-all-around cylindrical device shows many benefits over conventional multi-gate FinFET, including gate-all- around rectangular （GAAR） devices. With gate-all-around cylindrical architecture,the transistor is controlled by an essen- tially infinite number of gates surrounding the entire cylinder-shaped channel. The electrical integrity within the channel is improved by reducing the leakage current due to the non-symmetrical field accumulation such as the corner effect. The proposed fabrication procedures for devices having GAAC device architecture are also discussed. The method is characterized by its simplicity and full compatibility with conventional planar CMOS technology.
基金Project supported by the National Key Research and Development Program of China(Grant Nos.2016YFA0302300 and 2016YFA0200404)the National Natural Science Foundation of China(Grant No.61306105)+2 种基金the National Science and Technology Major Project of China(Grant No.2011ZX02708-002)the Tsinghua University Initiative Scientific Research Program,Chinathe Tsinghua National Laboratory for Information Science and Technology(TNList)Cross-discipline Foundation,China
文摘A simple process flow method for the fabrication of poly-Si nanowire thin film transistors（NW-TFTs） without advanced lithographic tools is introduced in this paper.The cross section of the nanowire channel was manipulated to have a parallelogram shape by combining a two-step etching process and a spacer formation technique.The electrical and temperature characteristics of the developed NW-TFTs are measured in detail and compared with those of conventional planar TFTs（used as a control）.The as-demonstrated NW-TFT exhibits a small subthreshold swing（191 mV/dec）,a high ON/OFF ratio（8.5 × 10~7）,alow threshold voltage（1.12 V）,a decreased OFF-state current,and a low drain-induced-barrier lowering value（70.11 mV/V）.The effective trap densities both at the interface and grain boundaries are also significantly reduced in the NW-TFT.The results show that all improvements of the NW-TFT originate from the enhanced gate controllability of the multi-gate over the channel.
文摘增强型氮化镓(GaN)基高电子迁移率晶体管(high electron mobility transistor,HEMT)是高频高功率器件与开关器件领域的研究热点,P-GaN栅技术因具备制备工艺简单、可控且工艺重复性好等优势而成为目前最常用且唯一实现商用的GaN基增强型器件制备方法。首先,概述了当前制约P-GaN栅结构GaN基HEMT器件发展的首要问题,从器件结构与器件制备工艺这2个角度,综述了其性能优化举措方面的最新研究进展。然后,通过对研究进展的分析,总结了当前研究工作面临的挑战以及解决方法。最后,对未来的发展前景、发展方向进行了展望。
