An analytical model for nanowire junctionless SOI FinFETs with considering three-dimensional coupling effect

In this paper, the three-dimensional （3D） coupling effect is discussed for nanowire junctionless silicon-on-insulator （SOI） FinFETs. With fin width decreasing from 100 nm to 7 nm, the electric field induced by the lateral gates increases and therefore the influence of back gate on the threshold voltage weakens. For a narrow and tall fin, the lateral gates mainly control the channel and therefore the effect of back gate decreases. A simple two-dimensional （2D） potential model is proposed for the subthreshold region of junctionless SO1 FinFET. TCAD simulations validate our model. It can be used to extract the threshold voltage and doping concentration. In addition, the tuning of back gate on the threshold voltage can be predicted.

Fin width and height dependence of bipolar amplification in bulk FinFETs submitted to heavy ion irradiation

FinFET technologies are becoming the mainstream process as technology scales down. Based on a 28-nm bulk p- FinFET device, we have investigated the fin width and height dependence of bipolar amplification for heavy-ion-irradiated FinFETs by 3D TCAD numerical simulation. Simulation results show that due to a well bipolar conduction mechanism rather than a channel （fin） conduction path, the transistors with narrower fins exhibit a diminished bipolar amplification effect, while the fin height presents a trivial effect on the bipolar amplification and charge collection. The results also indicate that the single event transient （SET） pulse width can be mitigated about 35% at least by optimizing the ratio of fin width and height, which can provide guidance for radiation-hardened applications in bulk FinFET technology.

15 nm Bulk nFinFET器件性能研究及参数优化

为研究Bulk FinFET工作时基本结构参数、器件温度和栅极材料对其性能的影响,建立了一个15 nm n型Bulk FinFET器件模型,仿真分析了不同栅长、鳍宽、鳍高、沟道掺杂浓度、器件工作温度、栅极材料对器件性能的影响,发现增长栅长、降低鳍宽和增加鳍高有助于抑制短沟道效应;1×10^(17)cm^(-3)以下的低沟道掺杂浓度对器件特性影响不大,但高掺杂会使器件失效;器件工作温度的升高会导致器件性能的下降;采用高K介质材料作为栅极器件性能优于传统材料SiO_(2)。

金属功函数波动效应快速预测方法及验证

金属功函数波动作为器件制造过程中的主要工艺波动源之一,其波动变化对器件电学特性有极大的影响。本文提出一种简便、快速预测半导体场效应管金属功函数波动效应的方法,并将其与商业软件中计算功函数波动的统计阻抗场法进行对比分析。参考IBM公司发布的14 nm SOI FinFET结构建立FinFET器件仿真模型并与实验数据对比验证后,引入金属功函数波动,分别用统计阻抗场法与本文提出的快速预测方法计算得到对应随机波动下模型的阈值电压V_(th)、关断电流I_(off)、工作电流I_(on)等电学特性参数的随机分布及这些参数结果的期望值、标准差、极差等统计参数,通过两者结果对比验证了快速预测方法的准确性。

未知工艺角下时序违反的机器学习预测

集成电路设计复杂性的增长以及工艺尺寸的持续缩减给静态时序分析以及设计周期带来了新的严峻挑战。为了提升静态时序分析效率、缩短设计周期,充分考虑FinFET工艺特性以及静态时序分析原理,提出了未知工艺角下时序违反的机器学习预测方法,实现了基于部分工艺角的时序特性来预测另外一部分工艺角的时序特性的目标。基于某工业设计进行实验,结果表明,提出的方法利用5个工艺角时序预测另外31个工艺角时序,可达到小于2 ps的平均绝对误差,远远优于传统方法所需的21个工艺角,显著改善了预测精度和减少了静态时序分析工作量。

Recent research development of FinFETs

The rapid development of CMOS technology is driven by the device scaling down. Classical MOS devices have encountered difficulties and challenges as scaling down to nanoscale [1], which seriously affects the device performance and limits the further development of CMOS technology.Because of the excellent control over short-channel effects and high current drive capability, novel multi-gate

SOI产业联盟发布SOI与体硅FinFETs的对比研究报告

在SOI产业联盟主要成员的支持下,SOI产业联盟发布SOI与体硅FinFETs的对比研究报告。

Impact of ambient temperature on the self-heating effects in FinFETs

We use an electro-thermal coupled Monte Carlo simulation framework to investigate the self-heating effect（SHE） in 14 nm bulk n Fin FETs with ambient temperature（TA） from 220 to 400 K. Based on this method, nonlocal heat generation can be achieved. Contact thermal resistances of Si/Metal and Si/Si O_2 are selected to ensure that the source and drain heat dissipation paths are the first two heat dissipation paths. The results are listed below：（i） not all input power（Q_（input） turns into heat generation in the device region and some is taken out by the thermal non-equilibrium carriers, owing to the serious non-equilibrium transport;（ii） a higher TA leads to a larger ratio of input power turning into heat generation in the device region at the same operating voltages;（iii） SHE can lead to serious degradation in the carrier transport, which will increase when TA increases;（iv） the current degradation can be 8.9% when Vds = 0.7 V, Vgs = 1 V and TA = 400 K;（v） device thermal resistance（Rth） increases with increasing of TA, which is seriously impacted by the non-equilibrium transport. Hence, the impact of TA should be carefully considered when investigating SHE in nanoscale devices.

Simulation analysis of heavy-ion-induced single-event response for nanoscale bulk-Si FinFETs and conventional planar devices

FinFET technologies are becoming the mainstream process as technology scales down.Based on 28-nm bulk-Si FinFETs

Simulation and characterization of stress in FinFETs using novel LKMC and nanobeam diffraction methods

A new simulation method and test instrument has been adopted to verify the traditional stress simulation in FinFET. First, a new algorithm named lattice kinetic Monte Carlo （LKMC） is used to simulate the SiGe epitaxy in source/drain regions and the stress distribution is consequently extracted after the LKMC simulation. Systematic comparison between the traditional polyhedron method and the LKMC method is carried out. The results confirm that extracted stress from both methods is consistent, which verifies the validity of traditional polyhedron method for the purpose of simulating stress in FinFET. In the following experiment, p-type FinFETs with SiGe stressors in source/drain regions are fabricated. The nano beam diffraction （NBD） method is employed to characterize the strain in Si fin. The strain value from the NBD test agrees well with the value extracted from traditional polyhedron simulation.

Device parameter optimization for sub-20nm node HK/MG-last bulk FinFETs

Sub-20 nm node bulk FinFET PMOS devices with an all-last high-k/metal gate （HK/MG） process are fabricated and the influence of a series of device parameters on the device scaling is investigated. The high and thin Fin structure with a tapered sidewall shows better performance than the normal Fin structure. The punch through stop layer （PTSL） and source drain extension （SDE） doping profiles are carefully optimized. The device without SDE annealing shows a larger drive current than that with SDE annealing due to better Si crystal regrowth in the amorphous Fin structure after source/drain implantation. The band-edged MG has a better short channel effect immunity, but the lower effective work function （EWF） MG shows a larger driveability. A tradeoff choice for different EWF MGs should be carefully designed for the device＇s scaling.

Analysis and performance exploration of high performance(HfO_2) SOI FinFETs over the conventional(Si_3N_4) SOI FinFET towards analog/RF design

Nowadays FinFET devices have replaced the MOS devices almost in all complex integrated circuits of electronic gadgets like computer peripherals, tablets, and smartphones in portable electronics. The scaling of FinFET is ongoing and the analog/RF performance is most affected by increased SCEs(short channel effects) in sub22 nm technology nodes. This paper explores the analog/RF performance study and analysis of high performance device-D2(conventional Hf02 spacer SOI FinFET) and device-D3(source/drain extended Hf02 spacer SOI FinFET) over the device-D1(conventional Si3 N4 spacer SOI FinFET) at 20 nm technology node through the 3-D(dimensional) simulation process. The major performance parameters like I(ON current), I(OFF current), gm(transconductance), gd(output conductance), A(intrinsic gain), SS(sub-threshold slope), TGF = g/I(trans-conductance generation factor), VEA(early voltage), GTFP(gain trans-conductance frequency product), TFP(tansconductance frequency product), GFP(gain frequency product), and f(cut-off frequency) are studied for evaluating the analog/RF performance of different flavored SOI FinFET structures. For analog performance evaluation,device-D3 and D2 give better results in terms of gm, ID(drain current) and SS parameters, and for RF performance evaluation device-D1 is better in terms of f, GTFP, TFP, and GFP parameters both at low and high values of V=0.05 V and V=0.7 V respectively.

Influence of gate-source/drain misalignment on the performance of bulk FinFETs by a 3D full band Monte Carlo simulation

We investigate the influence of gate-source/drain （G-S/D） misalignment on the performance of bulk fin field effect transistors （FinFETs） through the three-dimensional （3D） full band Monte Carlo simulator. Several scat- tering mechanisms, such as acoustic and optical phonon scattering, ionized impurity scattering, impact ionization scattering and surface roughness scattering are considered in our simulator. The influence of G-S/D overlap and underlap on the on-states performance and carrier transport of bulk FinFETs are mainly discussed in our work. Our results show that the on-states currents increase with the increment of G-D/S overlap length and the positions of a potential barrier and average electron energy maximum vary with the G-D/S overlap length. The carrier transport phenomena in bulk FinFETs are due to the effect of scattering and the electric field in the overlap/underlap regime.

基于青藏高原的14 nm FinFET和28 nm平面CMOS工艺SRAM单粒子效应实时测量试验

本文基于海拔为4300 m的拉萨羊八井国际宇宙射线观测站,开展了14 nm FinFET和28 nm平面互补金属氧化物半导体(complementary metal oxide semiconductor,CMOS)工艺静态随机存取存储器(static randomaccess memory,SRAM)阵列的大气辐射长期实时测量试验.试验持续时间为6651 h,共观测到单粒子翻转(single event upset,SEU)事件56个,其中单位翻转(single bit upset,SBU)24个,多单元翻转(multiple cell upset,MCU)32个.结合之前开展的65 nm工艺SRAM结果,研究发现,随着工艺尺寸的减小,器件的整体软错误率(soft error rate,SER)持续降低.但是,相比于65和14 nm工艺器件,28 nm工艺器件的MCU SER最大,其MCU占比(57%)超过SBU,MCU最大位数为16位.虽然14 nm FinFET器件的Fin间距仅有35 nm左右,且临界电荷降至亚fC,但FinFET结构的引入导致灵敏区电荷收集和共享机制发生变化,浅沟道隔离致使电荷扩散通道“狭窄化”,另一方面灵敏区表面积减小至0.0024μm^(2),从而导致14 nm工艺器件SBU和MCU的软错误率均明显下降.

大气中子及α粒子对芯片软错误的贡献趋势

在先进工艺集成电路中,高能中子、热中子和α粒子造成的软错误愈发受到关注。研究了150nm至16nmFinFET工艺节点器件在大气环境中的单粒子效应。随着工艺节点的缩小,高能中子引起的单粒子翻转截面和软错误率整体上均呈下降趋势。高能中子引起的软错误率在各个节点中均占据主导地位。热中子在45nm工艺节点下对软错误率有明显贡献,由其与W塞中所包含的10B核反应引起。α粒子在先进器件中的贡献整体出现下降趋势,在40nm工艺节点下出现极小值。此外,16nm工艺节点下FinFET结构的引入使集成电路的软错误率下降了一个数量级。

FinFET芯片TEM样品制备及避免窗帘效应方法

制备高质量纳米尺度芯片透射电子显微镜(TEM)样品对于探索半导体器件结构设计、材料分布与芯片性能之间的关系具有重要的意义。使用聚焦离子束(FIB)/扫描电子显微镜(SEM)双束系统制备14 nm鳍式场效应晶体管(FinFET)截面TEM样品,制备过程中从技术角度提出了两种自下而上制样方案来抑制窗帘效应。为扩大样品的可表征视场范围,在避免样品弯曲的前提下,提出了一种薄片提取方法。结果表明,离子束流越大,窗帘效应越严重,自下而上方法能有效规避窗帘效应;离子束电压30 kV时采用清洗截面(CCS)模式、5 kV/2 kV时采用矩形模式,样品台倾斜补偿角度为1.5°~3.5°,进行交叉减薄,且最终铣削长度控制在1μm时减薄效果最好;新的薄片提取方法改变了样品的铣削方向,在避免窗帘效应破坏感兴趣结构和样品弯曲的前提下,将样品的可表征视场范围扩大了5倍。研究结果对优化TEM样品制备方法以及芯片失效分析提供了参考。

Performance optimization of tri-gate junctionless FinFET using channel stack engineering for digital and analog/RF design

This manuscript explores the behavior of a junctionless tri-gate FinFET at the nano-scale region using SiGe material for the channel.For the analysis,three different channel structures are used:(a)tri-layer stack channel(TLSC)(Si-SiGe-Si),(b)double layer stack channel(DLSC)(SiGe-Si),(c)single layer channel(SLC)(S_(i)).The I−V characteristics,subthreshold swing(SS),drain-induced barrier lowering(DIBL),threshold voltage(V_(t)),drain current(ION),OFF current(IOFF),and ON-OFF current ratio(ION/IOFF)are observed for the structures at a 20 nm gate length.It is seen that TLSC provides 21.3%and 14.3%more ON current than DLSC and SLC,respectively.The paper also explores the analog and RF factors such as input transconductance(g_(m)),output transconductance(gds),gain(gm/gds),transconductance generation factor(TGF),cut-off frequency(f_(T)),maximum oscillation frequency(f_(max)),gain frequency product(GFP)and linearity performance parameters such as second and third-order harmonics(g_(m2),g_(m3)),voltage intercept points(VIP_(2),VIP_(3))and 1-dB compression points for the three structures.The results show that the TLSC has a high analog performance due to more gm and provides 16.3%,48.4%more gain than SLC and DLSC,respectively and it also provides better linearity.All the results are obtained using the VisualTCAD tool.

纳米FinFET的单粒子瞬态与Fin结构的相关性研究

工艺差异引起的Fin结构变化会造成纳米FinFET器件呈现不同的电学特性,使器件的单粒子瞬态效应(SET)复杂化。基于电学特性校准的14 nm SOI标准型FinFET器件,构建了弹头型、三角型、阶梯型、半圆型及底部椭圆型等5种结构,分析了SET的表征量与Fin结构参数间的相关性,并利用灰色理论,研究了它们之间的内在关联性。结果表明,器件的收集电荷量、沉积电荷量与Fin的截面积显著相关;SET电流峰值、电子-空穴对产生率峰值及双极放大系数同时依赖于Fin的截面积和等效沟道宽度,且对等效沟道宽度的依赖性更强。

Narrowed Si_(0.7)Ge_(0.3)channel FinFET with subthreshold swing of64 mV/Dec using cyclic self-limited oxidation and removal process

A narrowed Si_(0.7)Ge_(0.3)channel fin field-effect transistor(FinFET)device is demonstrated in detail by using an accuratecyclic wet treatment process.The Si_(0.7)Ge_(0.3)fin/per side of 0.63 nm in thickness can be accurately removed in each cycleby utilizing a self-limited oxidation with 40%HNO_(3)solution in 40 s and oxidation removal can be achieved with 1%HFsolution in 10 s.As a result,after the dummy gate removal,the fin width of Si_(0.7)Ge_(0.3)can be narrowed from 20 nm to 8 nmby utilizing 10 cycles of this wet treatment process.Compared with the conventional Si_(0.7)Ge_(0.3)FinFET under a similarprocess,the narrowed Si_(0.7)Ge_(0.3)channel FinFET can realize a strong gate control capability by using this newly developedwet treatment process,because its subthreshold slope can be reduced by 24%,improving from 87 mV/dec to 64 mV/dec.

Fin Field Effect Transistor with Active 4-Bit Arithmetic Operations in 22 nm Technology

A design of a high-speed multi-core processor with compact size is a trending approach in the Integrated Circuits(ICs)fabrication industries.Because whenever device size comes down into narrow,designers facing many power den-sity issues should be reduced by scaling threshold voltage and supply voltage.Initially,Complementary Metal Oxide Semiconductor(CMOS)technology sup-ports power saving up to 32 nm gate length,but further scaling causes short severe channel effects such as threshold voltage swing,mobility degradation,and more leakage power(less than 32)at gate length.Hence,it directly affects the arithmetic logic unit(ALU),which suffers a significant power density of the scaled multi-core architecture.Therefore,it losses reliability features to get overheating and increased temperature.This paper presents a novel power mini-mization technique for active 4-bit ALU operations using Fin Field Effect Tran-sistor(FinFET)at 22 nm technology.Based on this,a diode is directly connected to the load transistor,and it is active only at the saturation region as a function.Thereby,the access transistor can cutoff of the leakage current,and sleep transis-tors control theflow of leakage current corresponding to each instant ALU opera-tion.The combination of transistors(access and sleep)reduces the leakage current from micro to nano-ampere.Further,the power minimization is achieved by con-necting the number of transistors(6T and 10T)of the FinFET structure to ALU with 22 nm technology.For simulation concerns,a Tanner(T-Spice)with 22 nm technology implements the proposed design,which reduces threshold vol-tage swing,supply power,leakage current,gate length delay,etc.As a result,it is quite suitable for the ALU architecture of a high-speed multi-core processor.