Temperature-insensitive reading of a flash memory cell

The temperature characteristics of the read current of the NOR embedded flash memory with a 1.5T-per-cell structure are theoretically analyzed and experimentally verified.We verify that for a cell programmed with a“10”state,the read current is either increasing,decreasing,or invariable with the temperature,essentially depending on the reading overdrive voltage of the selected bitcell,or its programming strength.By precisely controlling the programming strength and thus manipulating its temperature coefficient,we propose a new setting method for the reference cells that programs each of reference cells to a charge state with a temperature coefficient closely tracking tail data cells,thereby solving the current coefficient mismatch and improving the read window.

Heavy ion induced upset errors in 90-nm 64 Mb NOR-type floating-gate Flash memory

Upset errors in 90-nm 64 Mb NOR-type floating-gate Flash memory induced by accelerated ^（129）Xe and ^（209）Bi ions are investigated in detail. The linear energy transfer covers the range from 50 to 99.8 Me V/（mg/cm^2）. When the memory chips are powered off during heavy ions irradiation, single-event-latch-up and single-event-function-interruption are excluded,and only 0-〉1 upset errors in the memory array are observed. These error bit rates seem very difficult to achieve and cannot be simply recovered based on the power cycle. The number of error bits shows a strong dependence on the linear energy transfer（LET）. Under room-temperature annealing conditions, the upset errors can be reduced by about two orders of magnitude using rewrite/reprogram operations, but they subsequently increase once again in a few minutes after the power cycle. High-temperature annealing can diminish almost all error bits, which are affected by the lower LET ^（129）Xe ions. The percolation path between the floating-gate（FG） and the substrate contributes to the radiation-induced leakage current, and has been identified as the root cause of the upset errors of the Flash memory array in this work.

Random telegraph noise on the threshold voltage of multi-level flash memory

We investigate the impact of random telegraph noise（RTN） on the threshold voltage of multi-level NOR flash memory.It is found that the threshold voltage variation（？Vth） and the distribution due to RTN increase with the programmed level（Vth） of flash cells. The gate voltage dependence of RTN amplitude and the variability of RTN time constants suggest that the large RTN amplitude and distribution at the high program level is attributed to the charge trapping in the tunneling oxide layer induced by the high programming voltages. A three-dimensional TCAD simulation based on a percolation path model further reveals the contribution of those trapped charges to the threshold voltage variation and distribution in flash memory.

Program Error Mitigation in MLC NAND Flash Memory with Soft Decision Decoders

Benefiting from strong decoding capabilities,soft-decision decoding has been used to replace hard-decision decoding in various communication systems,and NAND flash memory systems are no exception.However,soft-decision decoding relies heavily on accurate soft information.Owing to the incremental step pulse programming(ISPP),program errors(PEs)in multi-level cell(MLC)NAND flash memory have different characteristics compared to other types of errors,which is very difficult to obtain such accurate soft information.Therefore,the characteristics of the log-likelihood ratio(LLR)of PEs are investigated first in this paper.Accordingly,a PE-aware statistical method is proposed to determine the usage of PE mitigation schemes.In order to reduce the PE estimating workload of the controller,an adaptive blind clipping(ABC)scheme is proposed subsequently to approximate the PEs contaminated LLR with different decoding trials.Finally,simulation results demonstrate that(1)the proposed PE-aware statistical method is effective in practice,and(2)ABC scheme is able to provide satisfactory bit error rate(BER)and frame error rate(FER)performance in a penalty of negligible increasing of decoding latency.

Improvement of Operation Characteristics for MONOS Charge Trapping Flash Memory with SiGe Buried Channel

We propose and investigate a novel metal/SiO_2/Si_3N_4/SiO_2/SiGe charge trapping flash memory structure（named as MONOS）, utilizing Si Ge as the buried channel. The fabricated memory device demonstrates excellent programerasable characteristics attributed to the fact that more carriers are generated by the smaller bandgap of Si Ge during program/erase operations. A flat-band voltage shift 2.8 V can be obtained by programming at ＋11 V for 100 us. Meanwhile, the memory device exhibits a large memory window of ~7.17 V under ±12 V sweeping voltage, and a negligible charge loss of 18% after 104 s＇ retention. In addition, the leakage current density is lower than 2.52 × 10^（-7） A·cm^（-2） below a gate breakdown voltage of 12.5 V. Investigation of leakage current-voltage indicates that the Schottky emission is the predominant conduction mechanisms for leakage current. These desirable characteristics are ascribed to the higher trap density of the Si_3N_4 charge trapping layer and the better quality of the interface between the SiO_2 tunneling layer and the Si Ge buried channel. Therefore, the application of the Si Ge buried channel is very promising to construct 3 D charge trapping NAND flash devices with improved operation characteristics.

NEW Flash MEmory Products

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Optimized operation scheme of flash-memory-based neural network online training with ultra-high endurance

With the rapid development of machine learning,the demand for high-efficient computing becomes more and more urgent.To break the bottleneck of the traditional Von Neumann architecture,computing-in-memory(CIM)has attracted increasing attention in recent years.In this work,to provide a feasible CIM solution for the large-scale neural networks(NN)requiring continuous weight updating in online training,a flash-based computing-in-memory with high endurance(10^(9) cycles)and ultrafast programming speed is investigated.On the one hand,the proposed programming scheme of channel hot electron injection(CHEI)and hot hole injection(HHI)demonstrate high linearity,symmetric potentiation,and a depression process,which help to improve the training speed and accuracy.On the other hand,the low-damage programming scheme and memory window(MW)optimizations can suppress cell degradation effectively with improved computing accuracy.Even after 109 cycles,the leakage current(I_(off))of cells remains sub-10pA,ensuring the large-scale computing ability of memory.Further characterizations are done on read disturb to demonstrate its robust reliabilities.By processing CIFAR-10 tasks,it is evident that~90%accuracy can be achieved after 109 cycles in both ResNet50 and VGG16 NN.Our results suggest that flash-based CIM has great potential to overcome the limitations of traditional Von Neumann architectures and enable high-performance NN online training,which pave the way for further development of artificial intelligence(AI)accelerators.

Flash-based in-memory computing for stochastic computing in image edge detection

The“memory wall”of traditional von Neumann computing systems severely restricts the efficiency of data-intensive task execution,while in-memory computing(IMC)architecture is a promising approach to breaking the bottleneck.Although variations and instability in ultra-scaled memory cells seriously degrade the calculation accuracy in IMC architectures,stochastic computing(SC)can compensate for these shortcomings due to its low sensitivity to cell disturbances.Furthermore,massive parallel computing can be processed to improve the speed and efficiency of the system.In this paper,by designing logic functions in NOR flash arrays,SC in IMC for the image edge detection is realized,demonstrating ultra-low computational complexity and power consumption(25.5 fJ/pixel at 2-bit sequence length).More impressively,the noise immunity is 6 times higher than that of the traditional binary method,showing good tolerances to cell variation and reliability degradation when implementing massive parallel computation in the array.

A novel sourceline voltage compensation circuit for embedded NOR flash memory

A novel sourceline voltage compensation circuit for program operation in embedded flash memory is presented. With the sourceline voltage compensation circuit, the charge pump can modulate the output voltage according to the number of cells to be programmed with data ＂0＂. So the IR drop on the sourceline decoding path is compensated, and a stable sourceline voltage can be obtained. In order to reduce the power dissipation in program operation, a bit-inversion program circuit is adopted. By using the bit-inversion program circuit, the cells programmed to data ＂0＂ are limited to half of the bits of a write data word, thus power dissipation in program operation is greatly reduced. A 1.8-V 8 × 64-kbits embedded NOR flash memory employing the two circuits has been integrated using a GSMC 0.18-μm 4-poly 4-metal CMOS process.

A new low-voltage and high-speed sense amplifier for flash memory

A new low-voltage and high-speed sense amplifier is presented, based on a very simple direct currentmode comparison. It adopts low-voltage reference current extraction and a dynamic output method to realize its performance indicators such as low voltage, low power and high precision. The proposed amplifier can sense a 0.5 #A current gap and work with a lowest voltage of 1 V. In addition, the current power of a single amplifier is optimized by 15%.

A low-voltage sense amplifier for high-performance embedded flash memory

This paper presents a sense amplifier scheme for low-voltage embedded flash （eFlash） memory applications. The topology of the sense amplifier is based on current mode comparison. Moreover, an offset-voltage elimination technique is employed to improve the sensing performance under a small memory cell current. The proposed sense amplifier is designed based on a GSMC 130 nm eFlash process, and the sense time is 0.43 ns at 1.5 V, corresponding to a 46% improvement over the conventional technologies.

Non-volatile programmable homogeneous lateral MoTe2 junction for multi-bit flash memory and high-performance optoelectronics

Flash memories and semiconductor p-n junctions are two elementary but incompatible building blocks of most electronic and optoelectronic devices.The pressing demand to efficiently transfer massive data between memories and logic circuits,as well as for high data storage capability and device integration density,has fueled the rapid growth of technique and material innovations.Two-dimensional(2D)materials are considered as one of the most promising candidates to solve this challenge.However,a key aspect for 2D materials to build functional devices requires effective and accurate control of the carrier polarity,concentration and spatial distribution in the atomically thin structures.Here,a non-volatile opto-electrical doping approach is demonstrated,which enables reversibly writing spatially resolved doping patterns in the MoTe2 conductance channel through a MoTe2/hexagonal boron nitride(h-BN)heterostructure.Based on the doping effect induced by the combination of electrostatic modulation and ultraviolet light illumination,a 3-bit flash memory and various homojunctions on the same MoTe2/BN heterostructure are successfully developed.The flash memory achieved 8 well distinguished memory states with a maximum on/off ratio over 10^4.Each state showed negligible decay during the retention time of 2,400 s.The heterostructure also allowed the formation of p-p,n-n,p-n,and n-p homojunctions and the free transition among these states.The MoTe2 p-n homojunction with a rectification ratio of 10^3 exhibited excellent photodetection and photovoltaic performance.Having the memory device and p-n junction built on the same structure makes it possible to bring memory and computational circuit on the same chip,one step further to realize near-memory computing.

A low-voltage sense amplifier with two-stage operational amplifier clamping for flash memory

A low-voltage sense amplifier with reference current generator utilizing two-stage operational amplifier clamp structure for flash memory is presented in this paper,capable of operating with minimum supply voltage at1 V.A new reference current generation circuit composed of a reference cell and a two-stage operational amplifier clamping the drain pole of the reference cell is used to generate the reference current,which avoids the threshold limitation caused by current mirror transistor in the traditional sense amplifier.A novel reference voltage generation circuit using dummy bit-line structure without pull-down current is also adopted,which not only improves the sense window enhancing read precision but also saves power consumption.The sense amplifier was implemented in a flash realized in 90 run flash technology.Experimental results show the access time is 14.7 ns with power supply of 1.2 V and slow corner at 125℃.

Next High Performance and Low Power Flash Memory Package Structure

In general, NAND flash memory has advantages in low power consumption, storage capacity, and fast erase/write performance in contrast to NOR flash. But, main drawback of the NAND flash memory is the slow access time for random read operations. Therefore, we proposed the new NAND flash memory package for overcoming this major drawback. We present a high performance and low power NAND flash memory system with a dual cache memory. The proposed NAND flash package consists of two parts, i.e., an NAND flash memory module, and a dual cache module. The new NAND flash memory system can achieve dramatically higher performance and lower power consumption compared with any conventionM NAND-type flash memory module. Our results show that the proposed system can reduce about 78% of write operations into the flash memory cell and about 70% of read operations from the flash memory cell by using only additional 3KB cache space. This value represents high potential to achieve low power consumption and high performance gain.

A high efficiency all-PMOS charge pump for 3D NAND flash memory

For 3D vertical NAND flash memory, the charge pump output load is much larger than that of the planar NAND, resulting in the performance degradation of the conventional Dickson charge pump. Therefore, a novel all PMOS charge pump with high voltage boosting efficiency, large driving capability and high power efficiency for 3D V-NAND has been proposed. In this circuit, the Pellieoni structure is used to enhance the driving capability, two auxiliary substrate bias PMOS transistors are added to mitigate the body effect, and the degradation of the output voltage and boost efficiency caused by the threshold voltage drop is eliminated by dynamic gate control structure. Simulated results show that the proposed charge pump circuit can achieve the maximum boost efficiency of 86% and power efficiency of 50%. The output voltage of the proposed 9 stages charge pump can exceed 2 V under 2 MHz clock frequency in 2X nm 3D V-NAND technology. Our results provide guidance for the peripheral circuit design of high density 3D V-NAND integration.

Temperature self-adaptive program algorithm on 65nm MLC NOR flash memory

This paper presents an implementation for improving muti-level cell NOR flash memory program through-put based on the channel hot electron （CHE） temperature characteristic. The CHE Ig temperature characteristic is analyzed theoretically with the Lucky electron model, and a temperature self-adaptive programming algorithm is proposed to increase Ig according to the on-die temperature. Experimental results show that the program throughput increases significantly from 1.1 MByte/s without temperature self-adaptive programming to 1.4 MByte/s with the proposed method at room temperature. This represents a 30% improvement and is 70 times faster than the program throughput in Ref. [1].

Ultrafast flash memory with large self-rectifying ratio based on atomically thin MoS_(2)-channel transistor

Flash memory with high operation speed and stable retention performance is in great demand to meet the requirements of big data.In addition,the realisation of ultrafast flash memory with novel functions offers a means of combining heterogeneous components into a homogeneous device without considering impedance matching.This report proposes a 20 ns programme flash memory with 10^(8) self-rectifying ratios based on a 0.65 nm-thick MoS_(2)-channel transistor.A high-quality van der Waals heterojunction with a sharp interface is formed between the Cr/Au metal floating layer and h-BN tunnelling layer.In addition,the large rectification ratio and low ideality factor(n=1.13)facilitate the application of the MoS_(2)-channel flash memory as a bit-line select transistor.Finally,owing to the ultralow MoS_(2)/h-BN heterojunction capacitance(50 fF),the memory device exhibits superior performance as a high-frequency(up to 1 MHz)sine signal rectifier.These results pave the way toward the potential utilisation of multifunctional memory devices in ultrafast two-dimensional NAND-flash applications.

Adaptive in-page logging for flash-memory storage systems

Flash memory is widely used in embedded de- vices and enterprise storage systems. Currently, flash-based storage devices usually use a flash translation layer （FFL） to cope with the special features of flash memory. Many meth- ods for the design and implementation of the FTL have been proposed, such as BAST （block-associative sector transla- tion）, FAST （fully associative sector translation）, and IPL （in- page logging）, of which IPL has been demonstrated to have the best performance. However, IPL offers little considera- tion to reducing merge operations that consequently result in the degradation of the overall performance of flash-memory storage systems. We propose an improvement to IPL, called adaptive IPL （AIPL）. The idea of adaptive IPL is to make the log region in a block resizable, therefore a hot block （i.e., a write-intensive block） will use a large log region so as to absorb more page updates and in turn reduce the merge op- erations, while a cold block, i.e., a block rarely written to, will use a small log region. This is realized by first detecting the update pattern of a block and then presenting an update- pattern-based algorithm to dynamically adjust the log region size of a newly allocated block. We conduct experiments on TPC-C traces and synthetic traces and compare the perfor- mance of AIPL with other competitors in terms of merge count, write count and elapsed time. The results demonstrate that compared with IPL, AIPL can reduce merge operations by 65% and write operations by 54% on average.

改进的去隔行算法及FPGA验证平台设计

针对传统去隔行算法的不足,提出了一种改进的去隔行算法。该算法扩大了水平方向边缘搜索范围,并利用周围像素判断边缘,减小了误差,提高了小角度边缘搜索的精确度。为了验证算法的正确性,利用Altera公司的CycloneII FPGA结合SDRAM,Flash Memory构建了一个验证平台,该文介绍了平台组成框图,分析了各模块功能。实验结果表明,改进的算法弥补了传统算法边缘不够平滑,出现锯齿等缺点,验证平台也达到了预期要求。