In deep space exploration,many engineering and scientific requirements require the accuracy of the measured Doppler frequency to be as high as possible.In our paper,we analyze the possible frequency measurement points...In deep space exploration,many engineering and scientific requirements require the accuracy of the measured Doppler frequency to be as high as possible.In our paper,we analyze the possible frequency measurement points of the third-order phase-locked loop(PLL)and find a new Doppler measurement strategy.Based on this finding,a Doppler frequency measurement algorithm with significantly higher measurement accuracy is obtained.In the actual data processing,compared with the existing engineering software,the accuracy of frequency of 1 second integration is about 5.5 times higher when using the new algorithm.The improved algorithm is simple and easy to implement.This improvement can be easily combined with other improvement methods of PLL,so that the performance of PLL can be further improved.展开更多
针对常规基于二阶广义积分发生器的锁频环(second-order generalized integrator based frequency locked-loop,SOGI-FLL)在单相并网逆变器电压控制中对直流及谐波分量抑制能力不足,从而引起输出电压频率、相位振荡的问题,提出一种基于...针对常规基于二阶广义积分发生器的锁频环(second-order generalized integrator based frequency locked-loop,SOGI-FLL)在单相并网逆变器电压控制中对直流及谐波分量抑制能力不足,从而引起输出电压频率、相位振荡的问题,提出一种基于改进型SOGI-FLL的单相并网逆变器电压控制方法。该方法在常规SOGI-FLL控制的基础上,在电压信号输入端加入级联型谐振滤波环节来消除谐波分量;同时引入直流控制环节,借助输入电压误差估计值来消除直流分量,达到电网电压频率和相位快速跟踪效果,从而实现电压的自适应控制。使用MATLAB及RT-LAB硬件在环半实物平台,在频率突变、含直流分量及谐波分量的非理想电网环境中,对二阶广义积分器锁相环、双二阶广义积分器锁频环与改进型SOGI-FLL 3种控制方法进行仿真及实验。结果表明,所提改进型SOGI-FLL控制方法在消除直流及谐波干扰的同时,能在0.025 s内实现频率锁定,且频率偏差小于2%,可增强系统对非理想电网信号的适应能力,实现并网电压的快速跟踪,具有良好动态性能。展开更多
A design and implementation for a 2.4GHz quadrature output frequency synthesizer intended for bluetooth in 0. 35μm CMOS technology are presented. A differentially controlled quadrature voltage-controlled oscillator ...A design and implementation for a 2.4GHz quadrature output frequency synthesizer intended for bluetooth in 0. 35μm CMOS technology are presented. A differentially controlled quadrature voltage-controlled oscillator （QVCO） is employed to generate quadrature （I/Q） signals. A second-order loop filter, with a unit gain transconductance amplifier having the performance of a third-order loop filter,is exploited for low cost. The measured spot phase noise is -106.15dBc/Hz@ 1MHz. Close-in phase noise is less than -70dBc/Hz. The synthesizer consumes 13.5mA under a 3.3V voltage supply. The core size is 1.3mm×0. 8mm.展开更多
A fractional-N frequency synthesizer for 433/868MHz SRD applications is implemented in a 0.3μm CMOS process. A wide-band VCO and an AFC are used to cover the desired bands. A 3bit third order sigma-delta modulator is...A fractional-N frequency synthesizer for 433/868MHz SRD applications is implemented in a 0.3μm CMOS process. A wide-band VCO and an AFC are used to cover the desired bands. A 3bit third order sigma-delta modulator is adopted to reduce the out-band phase noise. The measurements show a VCO tuning range from 1.31 to 1.88GHz with AFC working correctly,an out-band phase noise of -139dBc/Hz at 3MHz offset frequency, and a fractional spur of less than - 60dBc. The chip area is 1.5mm × 1.2mm and the total current dissipation including LO buffers is 19mA from a single 3.0V supply voltage.展开更多
This paper presents an algorithm that aims to reduce the peak-to-average power ratio（PAPR） of orthogonal frequency division multiplexing（OFDM） communication systems while maintaining frequency tracking.The algorit...This paper presents an algorithm that aims to reduce the peak-to-average power ratio（PAPR） of orthogonal frequency division multiplexing（OFDM） communication systems while maintaining frequency tracking.The algorithm achieves PAPR reduction by applying the complex conjugates of the data symbol obtained from the frequency domain to cancel the phase of the data symbol.A likelihood estimator is used to obtain the sub-carrier phase error due to the residual carrier frequency offset（RCFO） using the same complex conjugates as a pilot signal.Furthermore,a joint time and frequency domain multicarrier phase locked loop（MPLL） is developed to compensate additional frequency offset.Simulation results show that this algorithm is capable of reducing PAPR without impacting the frequency tracking performance.展开更多
基金supported by the National Natural Science Foundation of China(Grant Nos.11773060,11973074,U1831137 and 11703070)National Key Basic Research and Development Program(2018YFA0404702)+1 种基金Shanghai Key Laboratory of Space Navigation and Positioning(3912DZ227330001)the Key Laboratory for Radio Astronomy of CAS。
文摘In deep space exploration,many engineering and scientific requirements require the accuracy of the measured Doppler frequency to be as high as possible.In our paper,we analyze the possible frequency measurement points of the third-order phase-locked loop(PLL)and find a new Doppler measurement strategy.Based on this finding,a Doppler frequency measurement algorithm with significantly higher measurement accuracy is obtained.In the actual data processing,compared with the existing engineering software,the accuracy of frequency of 1 second integration is about 5.5 times higher when using the new algorithm.The improved algorithm is simple and easy to implement.This improvement can be easily combined with other improvement methods of PLL,so that the performance of PLL can be further improved.
文摘针对常规基于二阶广义积分发生器的锁频环(second-order generalized integrator based frequency locked-loop,SOGI-FLL)在单相并网逆变器电压控制中对直流及谐波分量抑制能力不足,从而引起输出电压频率、相位振荡的问题,提出一种基于改进型SOGI-FLL的单相并网逆变器电压控制方法。该方法在常规SOGI-FLL控制的基础上,在电压信号输入端加入级联型谐振滤波环节来消除谐波分量;同时引入直流控制环节,借助输入电压误差估计值来消除直流分量,达到电网电压频率和相位快速跟踪效果,从而实现电压的自适应控制。使用MATLAB及RT-LAB硬件在环半实物平台,在频率突变、含直流分量及谐波分量的非理想电网环境中,对二阶广义积分器锁相环、双二阶广义积分器锁频环与改进型SOGI-FLL 3种控制方法进行仿真及实验。结果表明,所提改进型SOGI-FLL控制方法在消除直流及谐波干扰的同时,能在0.025 s内实现频率锁定,且频率偏差小于2%,可增强系统对非理想电网信号的适应能力,实现并网电压的快速跟踪,具有良好动态性能。
文摘A design and implementation for a 2.4GHz quadrature output frequency synthesizer intended for bluetooth in 0. 35μm CMOS technology are presented. A differentially controlled quadrature voltage-controlled oscillator （QVCO） is employed to generate quadrature （I/Q） signals. A second-order loop filter, with a unit gain transconductance amplifier having the performance of a third-order loop filter,is exploited for low cost. The measured spot phase noise is -106.15dBc/Hz@ 1MHz. Close-in phase noise is less than -70dBc/Hz. The synthesizer consumes 13.5mA under a 3.3V voltage supply. The core size is 1.3mm×0. 8mm.
文摘A fractional-N frequency synthesizer for 433/868MHz SRD applications is implemented in a 0.3μm CMOS process. A wide-band VCO and an AFC are used to cover the desired bands. A 3bit third order sigma-delta modulator is adopted to reduce the out-band phase noise. The measurements show a VCO tuning range from 1.31 to 1.88GHz with AFC working correctly,an out-band phase noise of -139dBc/Hz at 3MHz offset frequency, and a fractional spur of less than - 60dBc. The chip area is 1.5mm × 1.2mm and the total current dissipation including LO buffers is 19mA from a single 3.0V supply voltage.
基金supported by the National Natural Science Foundation of China(60872026)the Natural Science Foundation of Tianjin(09JCZDJC16900)
文摘This paper presents an algorithm that aims to reduce the peak-to-average power ratio（PAPR） of orthogonal frequency division multiplexing（OFDM） communication systems while maintaining frequency tracking.The algorithm achieves PAPR reduction by applying the complex conjugates of the data symbol obtained from the frequency domain to cancel the phase of the data symbol.A likelihood estimator is used to obtain the sub-carrier phase error due to the residual carrier frequency offset（RCFO） using the same complex conjugates as a pilot signal.Furthermore,a joint time and frequency domain multicarrier phase locked loop（MPLL） is developed to compensate additional frequency offset.Simulation results show that this algorithm is capable of reducing PAPR without impacting the frequency tracking performance.
