CMOS Direct-Injection Divide-by-3 Injection-Locked Frequency Dividers

This paper proposes CMOS LC-tank divide-by-3 injection locked frequency dividers(ILFDs)fabricated in 0.18μn and 90nm CMOS process and describes the circuit design,operation principle and measurement results of the ILFDs.The ILFDs use two injection series-MOSFETs across the LC resonator and a differential injection signal is applied to the gates of injection MOSFETs.The direct-injection divide-by-3 ILFDs are potential for radio-frequency application and can have wide locking range.

A 30GHz Wideband CMOS Injection-Locked Frequency Divider for 60GHz Transceiver

In this paper, a 30 GHz wide locking-range (26.2 GHz-35.7 GHz) direct injection-locked frequency divider (ILFD), which operating in the millimeter-wave (MMW) band, is presented. The locking range of the ILFD is extended by using differential injection topology. Besides, varactors are used in RLC resonant tank for extending the frequency tuning range. The post simulation results show that a wide locking-range of 9.5 GHz (30.7%) is achieved. When the VCO output frequency varies from 26.85 GHz to 34.42 GHz, the proposed ILFD can achieve divide-by-two correctly. Designed in 0.13 μm CMOS technology, the ILFD occupies a core area of 0.76 mm2 while drawing 7 mA of current from 2.5 V power supply.

A 31–45.5 GHz injection-locked frequency divider in 90-nm CMOS technology

We present a 31–45.5 GHz injection-locked frequency divider(ILFD) implemented in a standard 90-nm CMOS process. To reduce parasitic capacitance and increase the operating frequency, an NMOS-only cross-coupled pair is adopted to provide negative resistance. Acting as an adjustable resistor, an NMOS transistor with a tunable gate bias voltage is connected to the differential output terminals for locking range extension. Measurements show that the designed ILFD can be fully functional in a wide locking range and provides a good figure-of-merit. Under a 1 V tunable bias voltage, the self-resonant frequency of the divider is 19.11 GHz and the maximum locking range is 37.7% at 38.5 GHz with an input power of 0 d Bm. The power consumption is 2.88 m W under a supply voltage of 1.2 V. The size of the chip including the pads is 0.62 mm×0.42 mm.

基于40 nm CMOS工艺的毫米波注入锁定分频器

设计了一款应用于60GHz频率综合器的二分频注入锁定分频器。通过优化射频注入和直流偏置网络,降低了注入信号损耗,提高了注入效率;通过优化注入管和交叉管尺寸、减小寄生电容、降低振荡摆幅,提高了注入效率,降低了功耗;电磁仿真毫米波段电感,建立集总等效电路模型,实现了高感值、低串联电阻的差分电感的设计,提高了锁定范围。电路设计采用SMIC 40nm1P6M RF CMOS工艺,芯片核心面积为0.016mm2。仿真结果表明,在0.8V电源电压下,电路功耗为5.5mW,工作频率范围为55.2~61.2GHz,注入锁定范围为6.0GHz,满足低功耗和宽锁定范围的要求,适用于毫米波段锁相环频率综合器。

基于源耦合逻辑的正交二分频器设计

设计了一种基于源级耦合结构的正交二分频电路,由两个完全相同的源级耦合D触发器级联构成,交替工作于触发和锁存模式。对传统的源级耦合结构做了适当改进,采用动态负载,通过对PMOS管的开关控制很好地解决了电路工作速度和输出摆幅间的矛盾;且时钟开关PMOS和NMOS采用不同直流偏置,便于低电源电压下直流工作点的选取。采用TSMC 0.18μm RF CMOS工艺进行仿真验证。实验结果表明,分频器在1.92GHz输入时钟频率下能正常实现正交二分频,有较宽的锁定范围,且在3V电源电压下功耗仅为1.15mW。

用于Ka波段锁相环的宽带注入锁定分频器

基于0.13μm CMOS工艺,提出了一种用于Ka波段锁相环频率综合器的宽带注入锁定分频器。分析了传统注入锁定分频器的结构、自谐振频率和锁定范围。采用2位可变电容阵列和差分信号互补谐振腔直接注入方法,实现了宽带的注入锁定分频。仿真结果表明,当注入信号幅度Vp为0.6V时,该注入锁定分频器在24.1～35.6GHz频率范围内的锁定范围为38.5%。与VCO联合仿真,结果表明,该分频器能准确实现二分频,适用于Ka波段锁相环。

一种宽锁定范围的毫米波注入锁定分频器

基于GF 65nm CMOS工艺,实现了一种宽锁定范围的毫米波注入锁定(IL)分频器。采用电流复用前置放大器和双端混频,有效扩大了分频器的锁定范围,并且不产生额外的功耗。电路仿真结果表明,当调节电压在0~1.2V变化时,输入频率的锁定范围为81~110GHz。工作电压为0.8V时,电路的功耗为5.74mW。该分频器适用于75~110GHz的W-band系统。

一种应用于高速锁相环的宽锁定范围注入锁定分频器

针对传统的注入锁定分频器锁定范围较窄的问题,提出了一种用于毫米波锁相环的注入锁定分频器。基于55 nm CMOS工艺,设计了一种宽锁定范围的二分频注入锁定分频器。提出分布式差分注入的方式,增强注入电流与注入效率,采用高阶变压器作为谐振腔,在不使用调谐机制的条件下,有效增大了分频器的锁定范围。此外,还对传统buffer的结构进行改进,增强谐波抑制能力,保持了较宽的锁定范围。电路仿真结果表明,提出的分频器电路在0 dBm注入功率下可在22.8~36.3 GHz频段内完成二分频功能,达到45.7%的锁定范围,电路的功耗为3.54 mW(不含buffer)。

一种宽锁定范围多模2/3/4/5分频LC注入锁定分频器(英文)

提出了一种工作于3.55-12.15 GHz的2/3/4/5分频的注入锁定分频器(ILFD).该分频器使用了一种新颖的多模分频模块来提高注入节点的阻抗,从而增强高阶谐波并在4种分频比之间进行切换,同时保证每种分频比都具有较宽的锁定范围.在注入功率为0 d Bm的测试条件下,2/3/4/5分频的锁定范围分别是29.1%、29.3%、29.5%和29.9%.该分频器基于0.18μm CMOS工艺实现.总芯片面积和核心芯片面积分别是0.98×1.34mm2和0.32×0.84 mm^2.该分频器供电电压1.5 V,功耗为15 mW.