Key technologies of frequency-hopping frequency synthesizer for Bluetooth RF front-end

A scheme of a frequency-hopping frequency-synthesizer applied to a Bluetooth ratio frequency （RF） front-end is presented,and design of a voltage controlled oscillator （VCO） and dual-modulus prescaler are focused on.It is fabricated in a 0.18 μm mixed-signal CMOS （complementary metal-oxide-semiconductor transistor） process.The power dissipation of VCO is low and a stable performance is gained.The measured phase noise of VCO at 2.4 GHz is less than -114.32 dBc/Hz.The structure of the DMP is optimized and a novel D-latch integrated with ＂OR＂ logic gate is used.The measured results show that the chip can work well under a 1.8 V power supply.The power dissipation of the core part in a dual modulus prescaler is only 5.76 mW.An RMS jitter of 2 ps is measured on the output signal at 118.3 MHz.It is less than 0.02% of the clock period.

Design of Down Scalers in Mixed-Signal GHz Frequency Synthesizer

An optimized method is presented to design the down scalers in a GHz frequency synthesizer. The down scalers are comprised of dual modulus prescaler （DMP） and programmable ＆ pulse swallow divider,different methods of high frequency analog circuit and digital logical synthesis are adopted respectively. Using a DMP high speed, lower jitter and lower power dissipation are obtained,and output frequency of 133.0MHz of the DMP working at divide-by-8 shows an RMS jitter less than 2ps. The flexibility and reusability of the progrs, mmable divider is high;its use could be extended to many complicated frequency synthesizers. By comparison,it is a better design on performance of high-frequency circuit and good design flexibility.

A 2.4GHz Quadrature Output Frequency Synthesizer

A design and implementation for a 2.4GHz quadrature output frequency synthesizer intended for bluetooth in 0. 35μm CMOS technology are presented. A differentially controlled quadrature voltage-controlled oscillator （QVCO） is employed to generate quadrature （I/Q） signals. A second-order loop filter, with a unit gain transconductance amplifier having the performance of a third-order loop filter,is exploited for low cost. The measured spot phase noise is -106.15dBc/Hz@ 1MHz. Close-in phase noise is less than -70dBc/Hz. The synthesizer consumes 13.5mA under a 3.3V voltage supply. The core size is 1.3mm×0. 8mm.

A CMOS Fully Integrated Frequency Synthesizer with Stability Compensation

A complete closed-loop third order s-domain model is analyzed for a frequency synthesizer. Based on the model and root-locus technique, the procedure for parameters design is described, and the relationship between the process,voltage,and temperature variation of parameters and the loop stability is quantitatively analyzed. A variation margin is proposed for stability compensation. Furthermore,a simple adjustable current cell in the charge pump is proposed for additional stability compensation and a novel VCO with linear gain is adopted to limit the total variation. A fully integrated frequency synthesizer from 1 to 1.05GHz with 250kHz channel resolution is implemented to verify the methods.

Frequency synthesizer for DRM/DAB/AM/FM RF front-end

This paper describes a wideband low phase noise frequency synthesizer.It operates in the multi-band including digital radio mondiale DRM digital audio broadcasting DAB amplitude modulation AM and frequency modulation FM .In order to cover the signals of the overall frequencies a novel frequency planning and a new structure are proposed. A wide-band low-phase-noise low-power voltage-control oscillator VCO and a high speed wide band high frequency division ratio pulse swallow frequency divider with a low power consumption are presented.The monolithic DRM/DAB/AM/FM frequency synthesizer chip is also fabricated in a SMIC＇s 0.18-μm CMOS process.The die area is 1 425 μm ×795 μm including the test buffer and pads. The measured results show that the VCO operating frequency range is from 2.22 to 3.57 GHz the measured phase noise of the VCO is 120.22 dBc/Hz at 1 MHz offset the pulse swallow frequency divider operation frequency is from 0.9 to 3.4 GHz.The phase noise in the phase-locked loop PLL is-59.52 dBc/Hz at 10 kHz offset and fits for the demand of the DRM/DAB/AM/FM RF front-end. The proposed frequency synthesizer consumes 47 mW including test buffer under a 1.8 V supply.

A wideband low-phase-noise LC VCO for DRM/DAB frequency synthesizer

The wideband CMOS voltage-controlled oscillator（VCO）with low phase noise and low power consumption is presented for a DRM/DAB（digital radio mondiale and digital audio broadcasting）frequency synthesizer.In order to obtain a wide band and a large tuning range,a parallel switched capacitor bank is added in the LC tank.The proposed VCO is implemented in SMIC 0.18-μm RF CMOS technology and the chip area is 750 μm×560 μm,including the test buffer circuit and the pads.Measured results show that the tuning range is 44.6%;i.e.,the frequency turning range is from 2.27 to 3.57 GHz.The measured phase noise is-122.22 dBc/Hz at a 1 MHz offset from the carrier.The maximum power consumption of the core part is 6.16 mW at a 1.8 V power supply.

A Novel Method to Compensate the Sigma-Delta Shaped Noise for Wide Band Fractional-N Frequency Synthesizers

A novel method to partially compensate sigma-delta shaped noise is proposed. By injecting the compensation current into the passive loop filter during the delay time of the phase frequency detector（PFD）,a maximum reduction of the phase noise by about 16dB can be achieved. Compared to other compensation methods,the technique proposed here is relatively simple and easy to implement. Key building blocks for realizing the noise cancellation,including the delay variable PFD and compensation current source, are specially designed. Both the behavior level and circuit level simulation results are presented.

A Σ-Δ Fractional-N PLL Frequency Synthesizer with AFC for SRD Applications

A fractional-N frequency synthesizer for 433/868MHz SRD applications is implemented in a 0.3μm CMOS process. A wide-band VCO and an AFC are used to cover the desired bands. A 3bit third order sigma-delta modulator is adopted to reduce the out-band phase noise. The measurements show a VCO tuning range from 1.31 to 1.88GHz with AFC working correctly,an out-band phase noise of -139dBc/Hz at 3MHz offset frequency, and a fractional spur of less than - 60dBc. The chip area is 1.5mm × 1.2mm and the total current dissipation including LO buffers is 19mA from a single 3.0V supply voltage.

Digital Coarse Tuning Loop for Wide-Band Fast-Settling Dual-Loop Frequency Synthesizers

A new coarse tuning loop for a wide-band dual-loop frequency synthesizer is presented. The coarse tuning structure is composed of two digital modules, including a successive approximation register and a frequency comparator with a novel structure. The frequency comparator counts the prescaler cycles within a certain reference time and compares the number with preset data to estimate the VCO frequency. The frequency comparison error is analyzed in detail. Within a given coarse tuning time,our proposed structure shows a comparison error 20 times smaller than that of other reported structures. This structure also reuses the programmable divider as a part of the coarse tuning loop so that the circuit is greatly simplified.

A 1-GHz Charge Pump PLL Frequency Synthesizer for IEEE 1394b PHY

The design procedure of an 1-GHz phase-locked loop （PLL）-based frequency synthesizer used in IEEE 1394b physical （PHY） system is presented in this paper. The PLL＇s loop dynamics are analyzed in depth and theoretical relationships between all loop parameters are clearly described. All the parameters are derived and verified by Verilog-A model, which ensures the accuracy and efficiency of the circuit design and simulation. A 4-stage ring oscillator is employed to generate 1-GHz oscillation frequency and is divided into low frequency clocks by a feedback divider. The architecture is a third-order, type-2 charge pump PLL. The simulated settling time is less than 4μs. The RMS value of period jitter of the PLL＇s output is 2.1 ps. The PLL core occupies an area of 0.12 mm2, one fourth of which is occupied by the MiM loop capacitors. The total current consumption of the chip is 16.5 mA. The chip has been sent for fabrication in 0.13 μm complementary metal oxide semiconductor （CMOS） technology.

BIT COMMITMENT USING PSEUDO-RANDOM SYNTHESIZER

This paper presents two practical message commitment schemes: one is suitable for committing many bits, and another is useful for committing any bit-long message. They are provably secure based on pseudo-random synthesizers. In these schemes, the sender may be unbounded to polynomial time and the receiver is bounded. The advantage of these schemes is that the secure parameter may be small.

Frequency Synthesizer of Short-Wave SFH/MFSK System

The technology of DDS-driven PLL is introduced and a new scheme of frequency synthesizer which is suitable for SW SFH/MFSK System is presented in this paper. Based on the special requirement of SW communication, a model of the scheme is given and the results show that the frequency synthesizer has small frequency insteval (≤0.1 Hz), short switch pierod (<200 ms) and high frequency stability as crystal oseillator.

Fast Switching Fractional-N Frequency Synthesizer Architecture Using TDTL

This paper presents an efficient indirect fractional frequency synthesizer architecture based on the time delay digital tanlock loop. The indirect type frequency synthesis systems incorporate a low complexity high performance adaptation mechanism that enables them to remain in a locked state following the division process. The performance of the proposed fractional-N synthesizer under various input conditions is demonstrated. This includes sudden changes in the system input frequency as well as the injection of noise. The results of the extensive set of tests indicate that the fractional-N synthesizer, proposed in this work, performs well and is capable of achieving frequency divisions with fine resolution. The indirect frequency synthesizer also has a wide locking range and fast switching response. This is reflected by the system ability to regain its lock in response to relatively large variations in the input frequency within a few samples. The overall system performance shows high resilience to noise as reflected by the mean square error results.

TDTL Based Frequency Synthesizers with Auto Sensing Technique

This paper presents a frequency synthesizer architecture based on the time delay digital tanlock loop (TDTL). The loop is of the first order type. The synthesizer architecture includes an adaptation mechanism to keep the complete system in lock. The mechanism uses a frequency sensing structure to control critical TDTL parameters responsible for locking. Both integer and fractional multiples of the loop reference frequency are synthesized by the new architecture. The ability of the TDTL based frequency synthesizer to respond to sudden variations in the system input frequency is studied. The results obtained indicate the proposed synthesizer has a robust performance and is capable of responding to those changes provided that they are within the bounds of its locking region.

A 1.2-to-1.4 GHz low-jitter frequency synthesizer for GPS application

A fully integrated frequency synthesizer with low jitter and low power consumption in 0.18 μm CMOS (complementary metal-oxide semiconductor) technology is proposed in this paper.The frequency synthesizer uses a novel single-end gain-boosting charge pump, a differential coupled voltage controlled oscillator (VCO) and a dynamic logic phase/frequency detecor (PFD) to acquire low output jitter.The output frequency range of the frequency synthesizer is up to 1 200 MHz to 1 400 MHz for GPS (global position system) application.The post simulation results show that the phase noise of VCO is only 127.1 dBc/Hz at a 1 MHz offset and the Vp-p jitter of the frequency synthesizer output clock is 13.65 ps.The power consumption of the frequency synthesizer not including the divider is 4.8 mW for 1.8 V supply and it occupies a 0.8 mm×0.7 mm chip area.

EXACT ANALYSIS OF SPURIOUS SIGNALS IN DIRECT DIGITAL FREQUENCY SYNTHESIZERS DUE TO AMPLITUDE QUANTIZATION

Amplitude quantization is one of the main sources of spurious noise frequencies in Direct Digital Frequency Synthesizers (DDFSs), which affect their application to many wireless telecommu- nication systems. In this paper, two different kinds of spurious signals due to amplitude quantization in DDFSs are exactly formulated in the time domain and detailedly compared in the frequency do- main, and the effects of the DDFS parameter variations on the spurious performance are thoroughly studied. Then the spectral properties and power levels of the amplitude-quantization spurs in the absence of phase-accumulator truncation are emphatically analyzed by waveform estimation and computer simulation, and several important conclusions are derived which can provide theoretical support for parameter choice and spurious performance evaluation in the application of DDFSs.

COMPARISON OF SIGMA-DELTA MODULATOR FOR FRACTIONAL-N PLL FREQUENCY SYNTHESIZER

This paper investigates the design of digital Sigma-Delta Modulator (SDM) for fractional-N frequency synthesizer. Characteristics of SDMs are compared through theory analysis and simulation. The curve of maximum-loop-bandwidth vs. maximum-phase-noise is suggested to be a new criterion to the performance of SDM,which greatly helps designers to select an appropriate SDM structure to meet their real application requirements and to reduce the cost as low as possible. A low-spur 3-order Mul-tistage Noise Shaping (MASH)-1-1-1 SDM using three 2-bit first-order cascaded modulators is proposed,which balances the requirements of tone-free and maximum operation frequency.

Synthes线缆系统置入内固定治疗全髋关节置换后股骨假体周围骨折

背景:近年来股骨假体周围骨折已经成为是全髋关节置换后最常见的并发症之一,Vancourver B1型骨折因为股骨柄假体稳定同时无明显骨缺损,目前多主张积极行内固定治疗。目的:探讨Synthes线缆系统置入内固定治疗全髋关节置换后Vancouver B1型股骨假体周围骨折的临床效果。方法:2009年5月至2012年10月南通市第一人民医院骨科采用Synthes线缆系统置入内固定治疗18例全髋关节置换后Vancouver B1型股骨假体周围骨折患者,女10例,男8例;年龄45-80岁,平均(62.67±8.67)岁。治疗后第1,3,6个月复诊,按Harris评分标准评定髋关节功能,满分为100分,≥90分为优,80-89分为较好,70-79分为良,<70分为差。结果与结论:18例患者均获得随访,18例获得随访6-43个月,患者平均骨折愈合时间为(19.06±4.04)周。18例治疗前Harris评分为(22.3±3.6)分,治疗后第1,3,6个月髋关节Harris评分均较治疗前显著提高(P<0.01),髋关节功能恢复良好。提示Synthes线缆系统能最大程度恢复股骨正常解剖结构,操作简便,损伤小,稳定性强,安全性高,是治疗Vancouver B1型股骨假体周围骨折的理想方法。

Survey of Radiosensitizing Agents (Synthesized Chemicals and Gene Therapeutic Agents) Since 2000

Radiotherapy has played an important role in treatment of tumor patientssince it appeared about 80 years ago, and has been an indispensable part of the management of about50% of tumors (especially 60% - 70% of malignant tumors). Currently, radiotherapy is used in simpleand palliative therapy, adjuvant therapy after or before surgery, simultaneous radio-chemotherapy,combined BRM (biological response modifier) therapy, ets. Radiosensitizing agents enhance theradiation effects on tumor cells so as to have better responses in radiotherapy. Tumor intrinsicradiosensitivity is affected by the hy-poxic level in solid tumor, the ability of the cells torepair the radiation-induced DNA damage, the number of cells which have a clonogenic capability toreestablish uncontrolled cell growth, the amount of dividing cells, and the distribution of cellsthroughout the cell cycle. Consequently , it is necessary and useful to add one or moreradiosensitizing agents in radiotherapy to increase the radio-sensitivity of tumor cells.

鱼类褪黑素合成酶系编码基因的系统进化与生理功能

褪黑素是一种小分子神经递质,主要在脊椎动物的松果腺中合成与分泌,到达机体各部位来参与调控生物节律、生殖、生长与发育等生理过程。在鱼类中,松果腺是一个复合体,主要由类光感细胞构成,具有感光与内分泌双重功能。褪黑素的生物合成从色氨酸开始,涉及色氨酸羟化酶(TPH)、芳香族L-氨基酸脱羧酶(AAAD)、芳香烷胺-N-乙酰转移酶(AANAT)和乙酰色胺甲基转移酶(ASMT)。前期,我们通过对众多脊椎动物开展比较基因组学研究,发现这4个褪黑素合成酶系编码基因的系统进化与脊椎动物的物种进化基本一致,表明这些基因(同褪黑素一样)都很保守。有意思的是,在鱼类中各催化酶基因拷贝数出现显著增加,但四倍体与二倍体鱼中的拷贝数并不一定是2∶1,这是因为鱼类基因组复制后存在部分基因丢失的现象。此外,在大多数鱼类基因组中还鉴定到一些新基因,譬如aaad-like和asmt-like,可能拥有新的功能;有的催化酶基因缺失、出现移码突变或假基因化,可提升物种对特殊生境(诸如洞穴或深海)的生存适应性。本综述主要以我们团队近十年来的相关工作为主线,综合简介鱼类褪黑素合成酶系编码基因的系统进化与生理功能,以期深入理解褪黑素对鱼类生殖内分泌活动的影响,为进一步促进鱼类性腺发育、人工繁殖和分子育种等提供指导和支撑。