Multi-frequency point supported LLRF front-end for CiADS wide-bandwidth application

The China initiative Accelerator Driven System,CiADS,physics design adopts 162.5 MHz,325 MHz,and 650 MHz cavities,which are driven by the corresponding radio frequency(RF)power system,requiring frequency translation front-end for the RF station.For that application,a general-purpose design front-end prototype has been developed to evaluate the multi-frequency point supported design feasibility.The difficult parts to achieve the requirements of the general-purpose design are reasonable device selection and balanced design.With a carefully selected low-noise wide-band RF mixer and amplifier to balance the performance of multi-frequency supported down-conversion,specially designed LO distribution net to increase isolation between adjacent channels,and external band-pass filter to realize expected up-conversion frequencies,high maintenance and modular front-end generalpurpose design has been implemented.Results of standard parameters show an R2 value of at least 99.991%in the range of-60-10 dBm for linearity,up to 18 dBm for P1dB,and up to 89 dBc for cross talk between adjacent channels.The phase noise spectrum is lower than 80 dBc in the range of 0-1 MHz;cumulative phase noise is 0.006°;and amplitude and phase stability are 0.022%and 0.034°,respectively.

A single-ended wideband reconfigurable receiver front-end for multi-mode multi-standard applications in 0.18μm CMOS

This paper presents a reconfigurable RF front-end for multi-mode multi-standard(MMMS) applications. The designed RF front-end is fabricated in 0.18 μm RF CMOS technology. The low noise characteristic is achieved by the noise canceling technique while the bandwidth is enhanced by gate inductive peaking technique. Measurement results show that, while the input frequency ranges from 100 MHz to 2.9 GHz, the proposed reconfigurable RF front-end achieves a controllable voltage conversion gain(VCG) from 18 dB to 39 dB. The measured maximum input third intercept point(IIP3) is-4.9 dBm and the minimum noise figure(NF) is 4.6 dB. The consumed current ranges from 16 mA to 26.5 mA from a 1.8 V supply voltage. The chip occupies an area of 1.17 mm^2 including pads.

A tunable passive mixer for SAW-less front-end with reconfigurable voltage conversion gain and intermediate frequency bandwidth

An adjustable mixer for surface acoustic wave( SAW)-less radio frequency( RF) front-end is presented in this paper. Through changing the bias voltage,the presented mixer with reconfigurable voltage conversion gain( VCG) is suitable for multi-mode multi-standard( MMMS) applications. An equivalent local oscillator( LO) frequency-tunable high-Q band-pass filter( BPF) at low noise amplifier( LNA) output is used to reject the out-of-band interference signals. Base-band( BB) capacitor of the mixer is variable to obtain 15 kinds of intermediate frequency( IF) bandwidth( BW). The proposed passive mixer with LNA is implemented in TSMC 0. 18μm RF CMOS process and operates from 0. 5 to 2. 5 GHz with measured maximum out-of-band rejection larger than 40 d B. The measured VCG of the front-end can be changed from 5 to 17 d B; the maximum input intercept point( IIP3) is0 d Bm and the minimum noise figure( NF) is 3. 7 d B. The chip occupies an area of 0. 44 mm^2 including pads.

The front-end electronics design of dose monitors for beam delivery system of Shanghai Advanced Proton Therapy Facility

A front-end electronics of dose monitor has been developed for measuring irradiation dose to the patient in Shanghai Advanced Proton Therapy Facility.The parallel plate ionization chamber is used for the dose monitoring.Unlike the traditional method of recycling capacitor integration and voltage-to-frequency conversion,this dose monitor electronics uses the trans-impedance amplifier and analog-to-digital conversion method.It performs satisfactorily,with the integral nonlinearity of less than ±0.04 nA in the range of-400 to 50 nA and the resolution of about±0.6 nA.

Study of Reducing Non-Ideal Effects Based on TiN Sensitive Electrode with Front-End Offset Circuit

The structure of the extended gate ion sensitive field effect transistor (EGISFET) is similar to the structure of the ion sensitive field effect transistor (ISFET).Moreover,the non-ideal effect of EGISFET is the main impediment to development of commercial processes for sensitive devices.It is necessary to promote the stability and reliability of the devices by employing calibration circuits and the better fabrication conditions.The temporal drift exists in the entire measurement experiment. Furthermore,in this study we can reduce the temporal drift effect which influences the stability of the TiN sensitive electrode with the differential front-end offset circuit.The measurement system combines with shifting circuit,differential and instrument amplifiers.We employ the calibration circuit to compare with the variations of the output voltage,and expectably improve the stability and reliability of the TiN sensitive electrode by the novel calibration circuit.

Transforming Hand Drawn Wireframes into Front-End Code with Deep Learning

The way towards generating a website front end involves a designersettling on an idea for what kind of layout they want the website to have, thenproceeding to plan and implement each aspect one by one until they haveconverted what they initially laid out into its Html front end form, this processcan take a considerable time, especially considering the first draft of the designis traditionally never the final one. This process can take up a large amountof resource real estate, and as we have laid out in this paper, by using a Modelconsisting of various Neural Networks trained on a custom dataset. It can beautomated into assisting designers, allowing them to focus on the other morecomplicated parts of the system they are designing by quickly generating whatwould rather be straightforward busywork. Over the past 20 years, the boomin how much the internet is used and the sheer volume of pages on it demands ahigh level of work and time to create them. For the efficiency of the process, weproposed a multi-model-based architecture on image captioning, consisting ofConvolutional neural network (CNN) and Long short-term memory (LSTM)models. Our proposed approach trained on our custom-made database can beautomated into assisting designers, allowing them to focus on the other morecomplicated part of the system. We trained our model in several batches overa custom-made dataset consisting of over 6300 files and were finally able toachieve a Bilingual Evaluation Understudy (BLEU) score for a batch of 50hand-drawn images at 87.86%.

A New X-band Weather Radar System with Distributed Phased-Array Front-ends: Development and Preliminary Observation Results

A novel weather radar system with distributed phased-array front-ends was developed. The specifications and preliminary data synthesis of this system are presented, which comprises one back-end and three or more front-ends. Each front-end, which utilizes a phased-array digital beamforming technology, sequentially transmits four 22.5°-width beams to cover the 0°–90° elevational scan within about 0.05 s. The azimuthal detection is completed by one mechanical scan of0°–360° azimuths within about 12 s volume-scan update time. In the case of three front-ends, they are deployed according to an acute triangle to form a fine detection area(FDA). Because of the triangular deployment of multiple phased-array front-ends and a unique synchronized azimuthal scanning(SAS) rule, this new radar system is named Array Weather Radar(AWR). The back-end controls the front-ends to scan strictly in accordance with the SAS rule that assures the data time differences(DTD) among the three front-ends are less than 2 s for the same detection point in the FDA. The SAS can maintain DTD < 2 s for an expanded seven-front-end AWR. With the smallest DTD, gridded wind fields are derived from AWR data, by sampling of the interpolated grid, onto a rectangular grid of 100 m ×100 m ×100 m at a 12 s temporal resolution in the FDA. The first X-band single-polarized three-front-end AWR was deployed in field experiments in 2018 at Huanghua International Airport, China. Having completed the data synthesis and processing, the preliminary observation results of the first AWR are described herein.

A Broadband T/R Front-End of Millimeter Wave Holographic Imaging

A broadband T/R frond-end of active holographic imaging system is presented. Compact autodyne mode circuit structure front-end is adopted to achieve higher signal to noise ratio and higher reliability, which is beneficial to the after-end imagining. The factors that influence the dynamic range and the transverse resolution ratio of holographic imaging system have been analyzed. Wide-band oscillator, wide-band low noise amplifier and the tapered slot antennas are implemented to meet the requirements of the holographic imagining system. According to the measured results, the output power is uniform in the broadband working frequency. The sub-harmonic suppression is better than 25 dBc from the frequency of 28 GHz to 33 GHz. The isolation between antennas channel is greater than 20 dB. The experimental result shows that the performance of the front-end is good enough to meet the needs of active millimeter-wave holographic imaging system.

Front-end Control Mechanism of Electronic Records

In the digital era,how to ensure the authenticity and integrity of elec-tronic records has become an open challenging issue.Front-end control is an important concept as well as a basic principle in electronic record management.Under the instruction of front-end control,many original management links in the record-management stage are required to move forward,and the managers enter the formation stage of the electronic records to ensure the originality.How-ever,the front-end control technique primarily focuses on transaction manage-ment,and it lacks the strategy of providing the control of electronic records.In this paper,a novel electronic record front-end control mechanism is proposed by adopting proxy re-encryption and requiring archivists to participate in the man-agement of electronic records before the record is created to solve the problem.Specifically,when an electronic record is generated,the proposed mechanism interacts with the producer of the electronic record to generate a corresponding encryption key.Moreover,electronic records are encrypted by the key to protect their confidentiality,which can prevent the leakage of electronic record informa-tion.In addition,when transferring the electronic record,archivists use proxy re-encryption technology to convert electronic records,allowing management by an archivist,ensuring their originality and authenticity.

Design of a Novel Front-End Readout ASIC for PET Imaging System

The architecture of a multi-channel front-end system is important for realizing a high-resolution PET system. We propose a novel front-end readout electronic system with TDC to deal with time information for PET system which can easily design the timing control. Each channel consists of a charge preamplifier, slow/fast shaper, discriminator and an analog memory. There are an ADC and a TDC to process the energy information and time information for each channel at the same time. In this paper, the whole system signals flow is all simulated by MATLAB. The simulation results show that the proposed system can process slender current from the detector and achieve the energy and time information. The proposed architecture can be applied to high-resolution PET imaging systems with multi-channel ASICs.

Design of a Low-Noise Front-End Readout Circuit for CdZnTe Detectors

In this paper, the design of a novel low-noise front-end readout circuit for Cadmium zinc telluride (CdZnTe) X-ray and γ-ray detectors is described. The front-end readout circuits include the charge sensitive amplifier (CSA) and the CR-RC shaper is implemented in TSMC 0.35 μm mixed-signal CMOS technology. The die size of the prototype chip is 4.9 mm × 2.2 mm. The simulation results show that, the noise performance is 46 electrons + 10 electrons/pF, and power consumption is 1.65 mW per channel.

Reconfigurable Ultrasonic Testing System Development Using Programmable Analog Front-End and Reconfigurable System-on-Chip Hardware

Ultrasonic testing systems have been extensively used in medical imaging and non-destructive testing applications. Generally, these systems aim at a particular application or target material. To make these systems portable and more adaptable to the test environments, this study presents a reconfigurable ultrasonic testing system (RUTS), which possesses dynamic reconfiguration capabilities. RUTS consists a fully programmable Analog Front-End (AFE), which facilitates beamforming and signal conditioning for variety of applications. RUTS AFE supports up to 8 transducers for phased-array implementation. Xilinx Zynq System-on-Chip (SoC) based Zedboard provides the back-end processing of RUTS. The powerful ARM embedded processor available within Zynq SoC manages the ultrasonic data acquisition/processing and overall system control, which makes RUTS a unique platform for the ultrasonic researchers to experiment and evaluate a wide range of real-time ultrasonic signal processing applications. This Linux-based system is utilized for ultra-sonic data compression implementation providing a versatile environment for further development of ultrasonic imaging and testing system. Furthermore, this study demonstrates the capabilities of RUTS by performing ultrasonic data acquisition and data compression in real-time. Thus, this reconfigurable system enables ultrasonic designers and researchers to efficiently prototype different experiments and to incorporate and analyze high performance ultrasonic signal and image processing algorithms.

Design of a Low-Noise Front-End Readout CSP-Shaper System for CZT Detectors

This paper describes a low-noise front-end readout circuit for CZT detectors based on TSMC 0.35 um mixed-single CMOS technology;mainly analyzes the noise model of the detector-preamplifier and presents the low-noise circuit schematic of charge sensitive preamplifier and shaper. Considering the parasitical influences, the circuit and layout-design are optimized to reduce noise. The preliminary simulation results show that, the equivalent noise charge (ENC) is 74 e﹣ (rms), noise slope is 9 e﹣/pF, power consumption is 2 mW, and non-linearity

基于硅工艺的12GHz单片接收RF Front-End设计

提出了一种基于硅材料的、工作在12 GHz频率的用于接收卫星数字图像广播的单片射频前端系统,该系统含有低噪声放大器、混频器和第二级放大器,所有的电路都集成在硅材料工艺中,可以用于频率在12GHz的卫星通信频段信号的接收。

RF front-end for digital beam position monitor signal processor

RF circuit board has a significant impact on performance of the Digital Beam Position Monitor (DBPM) in storage ring of a synchrotron radiation facility.In this paper,a front-end RF board is designed for DBPM,and schematics of the RF board and the test results are given.In view of the inevitable inconsistency in the multi-channel circuit,a calibration circuit is designed to reduce such an influence.The test results show that the calibration method is useful for beam current dependence which is sensitive to channels inconsistency.

An analog front-end circuit for ISO/IEC 15693-compatible RFID transponder IC

The 13.56 MHz analog front-end circuit for ISO/IEC 15693-compatible radio frequency identification (RFID) trans- ponder IC presented in this paper converts RF power to DC and extracts clock and data from the interrogator by 10% or 100% ASK modulation. The transponder sends data back to the interrogator by load modulation technology. The electrostatic discharge (ESD) protection circuits function to limit RF voltage to a safe level. An inductive coupling simulation modelling for 13.56 MHz RFID system is presented, with simulation results showing that the transponder operates over a wide range of electromagnetic field strength from Hmin (150 mA/m) to Hmax (5 A/m). The transponder IC is implemented in SMIC 0.35-μm three-metal two-poly mixed signal CMOS technology with embedded EEPROM.

Polyphase Filter Banks for Embedded Sample Rate Changes in Digital Radio Front-Ends

This paper presents efficient processing engines for software-defined radio (SDR) front-ends. These engines, based on a polyphase channelizer, perform arbitrary sample-rate changes, frequency selection, and bandwidth control. This paper presents an M-path polyphase filter bank based on a modified N-path polyphase filter. Such a system allows resampling by arbitrary ratios while performing baseband aliasing from center frequencies at Nyquist zones that are not multiples of the output sample rate. This resampling technique is based on sliding cyclic data load interacting with cyclic-shifted coefficients. A non-maximally-decimated polyphase filter bank (where the number of data loads is not equal to the number of M subfilters) processes M subfilters in a time period that is less than or greater than the M data loads. A polyphase filter bank with five different resampling modes is used as a case study for embedded resampling in SDR front-ends. These modes are (i) maximally decimated, (ii) under-decimated, (iii) over-decimated, and combined up- and down-sampling with (iv) single stride length, and (v) multiple stride lengths. These modes can be used to obtain any required rational sampling rate change in an SDR front-end based on a polyphase channelizer. They can also be used for translation to and from arbitrary center frequencies that are unrelated to the output sample rates.

Upgrade to the front-end electronics of the BESⅢ muon identification system

Resistive Plate Chambers(RPCs) built from a new type of Bakelite developed at Institute of High Energy Physics(IHEP),Chinese Academy of Sciences have been used in the BESⅢ Muon identification system for several years without linseed oil coating,but characteristic aging performances were observed.To adapt to the RPCs in the aging state,the front-end electronics have been upgraded by enhancing the front-end protection,improving the threshold setting circuit,and separating power supplies of the comparator and the field programmable gate array(FPGA).Improvements in system stability,front-end protection and threshold consistency have been achieved.In this paper,the system upgrade and the test results are described in detail.

A versatile 16-channel front-end integrated circuit for semiconductor radiation detectors

A CMOS front-end integrated circuit consisting of 16 identical analog channels is proposed for semiconductor radiation detectors. Each of the 16 channels has a low noise charge sensitive amplifier, a pulse shaper, a peak detect and hold circuit and a discriminator, while analog voltage and channel address are routed off the chip. It can accommodate both electron and hole collection with selectable gain and peaking time. Sequential and sparse readout, combining with self-trigger and external trigger, makes four readout modes. The circuit is implemented in a 0.35 μm DP4M (double-poly-quad-metal) CMOS technology with an area of 2.5×1.54 mm2 and power dissipation of 60 mW. A single channel chip is tested with Verigy 93000. The gain is adjustable from 13 to 130 mV·fC–1 while the peaking time varies between 0.7 and 1.6 μs. The linearity is more than 99% and the equivalent noise charge is about 600e.

Front-end signal analysis of the transverse feedback system for SSRF

Multi-bunch instabilities degrade beam quality through increased beam emittance,energy spread and even cause beam loss.A feedback system is used to suppress multi-bunch instabilities associated with resistive wall of the beam ducts,cavity-like structures,and trapped ions.A digital TFS (Transverse Feedback System) is in construction at the SSRF (Shanghai Synchrotron Radiation Facility),which is based on the latest generation of FPGA (Field Programmable Gate Array) processor.Before we get such FPGA disital board,investigation and simulation of the front-end were done in the first place.The signal flow was analyzed by SystemView.Construction and optimization of the entire system is our next goal.