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Threshold Voltage Model for a Fully Depleted SOI-MOSFET with a Non-Uniform Profile
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作者 张国和 邵志标 周凯 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2007年第6期842-847,共6页
A novel approximation of the two-dimensional (2D) potential function perpendicular to the channel is proposed,and then an analytical threshold voltage model for a fully depleted SOI-MOSFET with a non-uniform Gaussia... A novel approximation of the two-dimensional (2D) potential function perpendicular to the channel is proposed,and then an analytical threshold voltage model for a fully depleted SOI-MOSFET with a non-uniform Gaussian distribution doping profile is given based on this approximation. The model agrees well with numerical simulation by MEDICI. The result represents a new way and some reference points in analyzing and controlling the threshold voltage of non-uniform fully depleted (FD) SOI devices in practice. 展开更多
关键词 fully depleted SOI-MOSFET NON-UNIFORM surface potential threshold voltage
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An Analytical Threshold Voltage Model for Fully Depleted SOI MOSFETs
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作者 李瑞贞 韩郑生 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2005年第12期2303-2308,共6页
A new two-dimensional (2D) analytical model for the threshold-voltage of fully depleted SOI MOSFETs is derived. The 2D potential distribution functions in the active layer of the devices are obtained through solving... A new two-dimensional (2D) analytical model for the threshold-voltage of fully depleted SOI MOSFETs is derived. The 2D potential distribution functions in the active layer of the devices are obtained through solving the 2D Poisson's equation. The minimum of the potential at the oxide-Si layer interface is used to monitor the threshold voltage of the SOI MOSFETs. This model is verified by its excellent agreement with MEDICI simulation using SOI MOSFETs with different gate lengths,gate oxide thicknesses,silicon film thicknesses,and channel doping concentrations. 展开更多
关键词 fully depleted SOI MOSFETs surface potential threshold voltage
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A Temperature-Dependent Model for Threshold Voltage and Potential Distribution of Fully Depleted SOI MOSFETs
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作者 唐俊雄 唐明华 +3 位作者 杨锋 张俊杰 周益春 郑学军 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2008年第1期45-49,共5页
A temperature-dependent model for threshold voltage and potential distribution of fully depleted silicon-on- insulator metal-oxide-semiconductor field-effect transistors is developed. The two-dimensional potential dis... A temperature-dependent model for threshold voltage and potential distribution of fully depleted silicon-on- insulator metal-oxide-semiconductor field-effect transistors is developed. The two-dimensional potential distribution function in the silicon thin film based on an approximate parabolic function has been applied to solve the two-dimensional Poisson's equation with suitable boundary conditions. The minimum of the surface potential is used to deduce the threshold voltage model. The model reveals the variations of potential distribution and threshold voltage with temperature, taking into account short-channel effects. Furthermore, the model is verified by the SILVACO ATLAS simulation. The calculations and the simulation agree well. 展开更多
关键词 fully depleted silicon-on-insulator MOSFETs POTENTIAL threshold voltage
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Simulation Study of Nanoscale FDSOI MOSFET Characteristics
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作者 Towhid Adnan Chowdhury 《Soft Nanoscience Letters》 2023年第3期13-22,共10页
Silicon on insulator (SOI) technology permits a good solution to the miniaturization as the MOSFET size scales down. This paper is about to compare the electrical performance of nanoscale FD-SOI MOSFET at various gate... Silicon on insulator (SOI) technology permits a good solution to the miniaturization as the MOSFET size scales down. This paper is about to compare the electrical performance of nanoscale FD-SOI MOSFET at various gate lengths. The performance is compared and contrasted with the help of threshold voltage, subthreshold slope, on-state current and leakage current. Interestingly, by decreasing the gate length, the leakage current and on-state current are increased but the threshold voltage is decreased and the sub-threshold slope is degraded. Silvaco two-dimensional simulations are used to analyze the performance of the proposed structures. 展开更多
关键词 fully Depleted Silicon on Insulator Threshold Voltage Subthreshold Slope Leakage Current Gate Length
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SOICMOS Integrated Circuit of Laser Range Finding Working at High Temperatures
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作者 高勇 张新 +3 位作者 刘梦新 安涛 刘善喜 马立国 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2007年第2期159-165,共7页
Modeling analysis of thin fully depleted SOICMOS technology has been done. Using ISETCAD software,the high temperature characteristics of an SOICMOS transistor were simulated in the temperature range of from 300 to 60... Modeling analysis of thin fully depleted SOICMOS technology has been done. Using ISETCAD software,the high temperature characteristics of an SOICMOS transistor were simulated in the temperature range of from 300 to 600K, and the whole circuit of a laser range finder was simulated with Verilog software. By wafer pro- cessing,a circuit of a laser range finder with complete function and parameters working at high temperatures has been developed. The simulated results agree with the test results. The test of the circuit function and parameters at normal and high temperature shows the realization of an SOICMOS integrated circuit with low power dissipation and high speed, which can be applied in laser range finding. By manufacturing this device, further study on high temperature characteristics of shorter channel SOICMOS integrated circuits can be conducted. 展开更多
关键词 silicon on insulator high temperature characteristics TRANSISTOR thin fully depleted
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Fully depleted vdW heterojunction based high performance photovoltaic photodetector 被引量:1
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作者 Yonghong Zeng Fanxu Meng +14 位作者 Sidi Fan Pengfei Wang Cuiyun Kou Mingyi Sun Haiguo Hu Rui Cao Swelm Wageh Omar A.Al-Hartomy Abul Kalam Bowen Du Wenchao Ding Songrui Wei Zhinan Guo Qiuliang Wang Han Zhang 《Journal of Materiomics》 SCIE CSCD 2023年第6期1039-1047,共9页
Van der Waals(vdW)heterojunctions,with their unique electronic and optoelectronic properties,have become promising candidates for photodetector applications.Amplifying the contribution of the depletion region in vdW h... Van der Waals(vdW)heterojunctions,with their unique electronic and optoelectronic properties,have become promising candidates for photodetector applications.Amplifying the contribution of the depletion region in vdW heterojunction,which would enhance both of the collection efficiency and speed of the photogenerated carriers,presents an effective strategy for achieving high performance vdW heterojunction photodetectors.Herein,a fully depleted vdW heterojunction photodetector is built on two-dimensional(2D)semiconductor materials(GaTe and InSe)layered on a pattered bottom electrode in vertical structure,in which the generation and motion of carriers are exclusively achieved in the depletion region.Attributed to the intrinsic built-in electric field,the elimination of series resistance and the depletion region confinement of carriers,the as-fabricated photodetector exhibits prominent photovoltaic properties with a high open-circuit voltage of 0.465 V,as well as photoresponse characteristics with outstanding responsivity,detectivity and photoresponse speed of 63.7 A/W,3.88×10^(13)Jones,and 32.7 ms respectively.The overall performance of this fully depleted GaTe/InSe vdW heterojunctions photodetectors are ranking high among the top level of 2D materials based photodetectors.It indicates the device architecture can provide new opportunities for the fabrication of high-performance photodetectors. 展开更多
关键词 Two-dimensional material van der waals heterojunction fully depleted photodetector PHOTOVOLTAIC
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Heteromaterial-gate line tunnel field-effect transistor based on Si/Ge heterojunction
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作者 Shuqin Zhang Renrong Liang +2 位作者 Jing Wang Zhen Tan Jun Xu 《Chinese Physics B》 SCIE EI CAS CSCD 2017年第1期557-562,共6页
A Si/Ge heterojunction line tunnel field-effect transistor (LTFET) with a symmetric heteromaterial gate is proposed. Compared to single-material-gate LTFETs, the heteromaterial gate LTFET shows an off-state leakage ... A Si/Ge heterojunction line tunnel field-effect transistor (LTFET) with a symmetric heteromaterial gate is proposed. Compared to single-material-gate LTFETs, the heteromaterial gate LTFET shows an off-state leakage current that is three orders of magnitude lower, and steeper subthreshold characteristics, without degradation in the on-state current. We reveal that these improvements are due to the induced local potential barrier, which arises from the energy-band profile modulation effect. Based on this novel structure, the impacts of the physical parameters of the gap region between the pocket and the drain, including the work-function mismatch between the pocket gate and the gap gate, the type of dopant, and the doping concentration, on the device performance are investigated. Simulation and theoretical calculation results indicate that the gap gate material and n-type doping level in the gap region should be optimized simultaneously to make this region fully depleted for further suppression of the off-state leakage current. 展开更多
关键词 line tunnel field-effect transistor heteromaterial gate fully depleted
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Analytical modeling of drain current and RF performance for double-gate fully depleted nanoscale SOI MOSFETs 被引量:1
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作者 Rajiv Sharma Sujata Pandey Shail Bala Jain 《Journal of Semiconductors》 EI CAS CSCD 2012年第2期28-35,共8页
A new 2D analytical drain current model is presented for symmetric double-gate fully depleted nanoscale SOI MOSFETs.Investigation of device parameters like transconductance for double-gate fully depleted nanoscale SOI... A new 2D analytical drain current model is presented for symmetric double-gate fully depleted nanoscale SOI MOSFETs.Investigation of device parameters like transconductance for double-gate fully depleted nanoscale SOI MOSFETs is also carried out.Finally this work is concluded by modeling the cut-off frequency, which is one of the main figures of merit for analog/RF performance for double-gate fully depleted nanoscale SOI MOSFETs.The results of the modeling are compared with those obtained by a 2D ATLAS device simulator to verify the accuracy of the proposed model. 展开更多
关键词 DOUBLE-GATE fully depleted SILICON-ON-INSULATOR Poisson's equation radio frequency ATLAS
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X-ray irradiation-induced degradation in Hf_(0.5)Zr_(0.5)O_(2) fully depleted silicon-on-insulator n-type metal oxide semiconductor field-effect transistors 被引量:1
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作者 Yu-Dong Li Qing-Zhu Zhang +5 位作者 Fan-Yu Liu Zhao-Hao Zhang Feng-Yuan Zhang Hong-Bin Zhao Bo Li Jiang Yan 《Rare Metals》 SCIE EI CAS CSCD 2021年第11期3299-3307,共9页
The n-type ultrathin fully depleted silicon-on-insulator(FDSOI) metal-oxide-semiconductor field-effect transistors(MOSFETs),with a Hf_(0.5)Zr_(0.5)O_(2) high dielectric permittivity(high-k) dielectric as gate insulato... The n-type ultrathin fully depleted silicon-on-insulator(FDSOI) metal-oxide-semiconductor field-effect transistors(MOSFETs),with a Hf_(0.5)Zr_(0.5)O_(2) high dielectric permittivity(high-k) dielectric as gate insulator,were fabricated.The total ionizing dose effects were investigated,and an X-ray radiation dose up to 1500 krad(Si) was applied for both long-and short-channel devices.The short-channel devices(0.025-0.100 μm) exhibited less irradiation sensitivity compared with the long-channel devices(0.35-16 μm),leading to a 71% reduction in the irradiation-induced drain current growth and a 26% decrease in the shift of the threshold voltage.It was experimentally demonstrated that the OFF mode is the worst case among the three working conditions(OFF,ON and A110) for short-channel devices.Also,the determined effective electron mobility was enhanced by 38% after X-ray irradiation,attributed to the different compensations for charges triggered by radiation between the highk dielectric and buried oxide.By extracting the carrier mobility,gate length modulation,and source/drain(S/D)parasitic resistance,the degradation mechanism on X-ray irradiation was revealed.Finally,the split capacitance-voltage measurements were used to validate the analysis. 展开更多
关键词 Total ionizing dose fully depleted silicon-on-insulator(FDSOI) Metal–oxide–semiconductor field-effect transistor(MOSFET) HIGH-K Hf_(0.5)Zr_(0.5)O_(2)
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Digital 1 V 82 μW Pseudo-Two-Stage Class-AB OTA
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作者 殷树娟 孙义和 李翔宇 《Tsinghua Science and Technology》 SCIE EI CAS 2009年第5期601-605,共5页
A low power digital operational transconductance amplifier (OTA) was developed for low voltage switched capacitor applications. The OTA has a high slew rate (SR) and a large open loop gain with a dif- ferential ps... A low power digital operational transconductance amplifier (OTA) was developed for low voltage switched capacitor applications. The OTA has a high slew rate (SR) and a large open loop gain with a dif- ferential pseudo-two-stage Class-AB structure. A fully compensated depletion mode capacitor is used in the switched capacitor common mode feedback block instead of a metal-insulator-metal (MIM) capacitor to reduce the fabrication cost. Simulations show that with a 1.0-V supply voltage and a 34-pF load at each output terminal, this digital differential pseudo-two-stage Class-AB OTA realized in 0.13-μm technology achieves a 63.5-dB DC gain and a 0.83-V output swing. The slew rate is ±16.29V/μs and the total power dissipation is only 82 μW. 展开更多
关键词 low voltage low power operational transconductance amplifier (OTA) fully compensated depletion mode MOS-capacitor CLASS-AB
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On substrate dopant engineering for ET-SOI MOSFETs with UT-BOX
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作者 吴昊 许淼 +6 位作者 万光星 朱慧珑 赵利川 童小东 赵超 陈大鹏 叶甜春 《Journal of Semiconductors》 EI CAS CSCD 2014年第11期64-69,共6页
The importance ofsubstrate doping engineering for extremely thin SOI MOSFETs with ultra-thin buried oxide (ES-UB-MOSFETs) is demonstrated by simulation. A new substrate/backgate doping engineering, lateral non-unifo... The importance ofsubstrate doping engineering for extremely thin SOI MOSFETs with ultra-thin buried oxide (ES-UB-MOSFETs) is demonstrated by simulation. A new substrate/backgate doping engineering, lateral non-uniform dopant distributions (LNDD) is investigated in ES-UB-MOSFETs. The effects of LNDD on device performance, Vt-roll-off, channel mobility and random dopant fluctuation (RDF) are studied and optimized. Fixing the long channel threshold voltage (Vt) at 0.3 V, ES-UB-MOSFETs with lateral uniform doping in the substrate and forward back bias can scale only to 35 nm, meanwhile LNDD enables ES-UB-MOSFETs to scale to a 20 nm gate length, which is 43% smaller. The LNDD degradation is 10% of the carrier mobility both for nMOS and pMOS, but it is canceled out by a good short channel effect controlled by the LNDD. Fixing Vt at 0.3 V, in long channel devices, due to more channel doping concentration for the LNDD technique, the RDF in LNDD controlled ES-UB-MOSFETs is worse than in back-bias controlled ES-UB-MOSFETs, but in the short channel, the RDF for LNDD controlled ES-UB-MOSFET is better due to its self-adaption of substrate doping engineering by using a fixed thickness inner-spacer. A novel process flow to form LNDD is proposed and simulated. 展开更多
关键词 extremely thin SOl (ETSOI) fully depleted SOI (FDSOI) short channel effect ultra thin BOX (UT- BOX)
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