We fabricated a set of symmetric gate-recess devices with gate length of 70 nm.We kept the source-to-drain spacing(L_(SD))unchanged,and obtained a group of devices with gate-recess length(L_(recess))from 0.4µm to...We fabricated a set of symmetric gate-recess devices with gate length of 70 nm.We kept the source-to-drain spacing(L_(SD))unchanged,and obtained a group of devices with gate-recess length(L_(recess))from 0.4µm to 0.8µm through process improvement.In order to suppress the influence of the kink effect,we have done SiN_(X) passivation treatment.The maximum saturation current density(ID_(max))and maximum transconductance(g_(m,max))increase as L_(recess) decreases to 0.4µm.At this time,the device shows ID_(max)=749.6 mA/mm at V_(GS)=0.2 V,V_(DS)=1.5 V,and g_(m,max)=1111 mS/mm at V_(GS)=−0.35 V,V_(DS)=1.5 V.Meanwhile,as L_(recess) increases,it causes parasitic capacitance C_(gd) and g_(d) to decrease,making f_(max) drastically increases.When L_(recess)=0.8µm,the device shows f_(T)=188 GHz and f_(max)=1112 GHz.展开更多
The performance degradation of gate-recessed metal–oxide–semiconductor high electron mobility transistor(MOSHEMT)is compared with that of conventional high electron mobility transistor(HEMT)under direct current(DC)s...The performance degradation of gate-recessed metal–oxide–semiconductor high electron mobility transistor(MOSHEMT)is compared with that of conventional high electron mobility transistor(HEMT)under direct current(DC)stress,and the degradation mechanism is studied.Under the channel hot electron injection stress,the degradation of gate-recessed MOS-HEMT is more serious than that of conventional HEMT devices due to the combined effect of traps in the barrier layer,and that under the gate dielectric of the device.The threshold voltage of conventional HEMT shows a reduction under the gate electron injection stress,which is caused by the barrier layer traps trapping the injected electrons and releasing them into the channel.However,because of defects under gate dielectrics which can trap the electrons injected from gate and deplete part of the channel,the threshold voltage of gate-recessed MOS-HEMT first increases and then decreases as the conventional HEMT.The saturation phenomenon of threshold voltage degradation under high field stress verifies the existence of threshold voltage reduction effect caused by gate electron injection.展开更多
A two-step gate-recess process combining high selective wet-etching and non-selective digital wet-etching techniques has been proposed for InAlAs/InGaAs InP-based high electron mobility transistors （HEMTs）. High etc...A two-step gate-recess process combining high selective wet-etching and non-selective digital wet-etching techniques has been proposed for InAlAs/InGaAs InP-based high electron mobility transistors （HEMTs）. High etching-selectivity ratio of InGaAs to InA1As material larger than 100 is achieved by using mixture solution of succinic acid and hydrogen peroxide （H202）. Selective wet-etching is validated in the gate-recess process of InA1As/InGaAs InP-based HEMTs, which proceeds and auto- matically stops at the InA1As barrier layer. The non-selective digital wet-etching process is developed using a separately controlled oxidation/de-oxidation technique, and during each digital etching cycle 1.2 nm InAIAs material is removed. The two-step gate-recess etching technique has been successfully incorporated into device fabrication. Digital wet-etching is repeated for two cycles with about 3 nm InAIAs barrier layer being etched off. InP-based HEMTs have demonstrated superior extrinsic trans- conductance and RF characteristics to devices fabricated during only the selective gate-recess etching process because of the smaller gate to channel distance.展开更多
In this paper, in order to solve the interface-trap issue and enhance the transconductance induced by high-k dielectric in metal-insulator-semiconductor （MIS） high electron mobility transistors （HEMTs）, we demonst...In this paper, in order to solve the interface-trap issue and enhance the transconductance induced by high-k dielectric in metal-insulator-semiconductor （MIS） high electron mobility transistors （HEMTs）, we demonstrate better performances of recessed-gate A1203 MIS-HEMTs which are fabricated by Fluorine-based Si3N4 etching and chlorine- based A1CaN etching with three etching times （15 s, 17 s and 19 s）. The gate leakage current of MIS-HEMT is about three orders of magnitude lower than that of A1GaN/CaN HEMT. Through the recessed-gate etching, the transconductanee increases effectively. When the recessed-gate depth is 1.02 nm, the best interface performance with Tit----（0.20--1.59） p^s and Dit ：（0.55-1.08）x 1012 cm-2.eV- 1 can be obtained. After chlorine-based etching, the interface trap density reduces considerably without generating any new type of trap. The accumulated chlorine ions and the N vacancies in the AIGaN surface caused by the plasma etching can degrade the breakdown and the high frequency performances of devices. By comparing the characteristics of recessed-gate MIS-HEMTs with different etching times, it is found that a low power chlorine-based plasma etching for a short time （15 s in this paper） can enhance the performances of MIS-HEMTs effectively.展开更多
基金the National Natural Science Foundation of China(Grant No.61434006).
文摘We fabricated a set of symmetric gate-recess devices with gate length of 70 nm.We kept the source-to-drain spacing(L_(SD))unchanged,and obtained a group of devices with gate-recess length(L_(recess))from 0.4µm to 0.8µm through process improvement.In order to suppress the influence of the kink effect,we have done SiN_(X) passivation treatment.The maximum saturation current density(ID_(max))and maximum transconductance(g_(m,max))increase as L_(recess) decreases to 0.4µm.At this time,the device shows ID_(max)=749.6 mA/mm at V_(GS)=0.2 V,V_(DS)=1.5 V,and g_(m,max)=1111 mS/mm at V_(GS)=−0.35 V,V_(DS)=1.5 V.Meanwhile,as L_(recess) increases,it causes parasitic capacitance C_(gd) and g_(d) to decrease,making f_(max) drastically increases.When L_(recess)=0.8µm,the device shows f_(T)=188 GHz and f_(max)=1112 GHz.
基金the Laboratory Open Fund of Beijing Smart-chip Microelectronics Technology Co.Ltd and the National Natural Science Foundation of China(Grant No.11690042)+1 种基金the Science Challenge Project,China(Grant Nos.TZ2018004 and 12035019)the National Major Scientific Research Instrument Projects,China(Grant No.61727804)。
文摘The performance degradation of gate-recessed metal–oxide–semiconductor high electron mobility transistor(MOSHEMT)is compared with that of conventional high electron mobility transistor(HEMT)under direct current(DC)stress,and the degradation mechanism is studied.Under the channel hot electron injection stress,the degradation of gate-recessed MOS-HEMT is more serious than that of conventional HEMT devices due to the combined effect of traps in the barrier layer,and that under the gate dielectric of the device.The threshold voltage of conventional HEMT shows a reduction under the gate electron injection stress,which is caused by the barrier layer traps trapping the injected electrons and releasing them into the channel.However,because of defects under gate dielectrics which can trap the electrons injected from gate and deplete part of the channel,the threshold voltage of gate-recessed MOS-HEMT first increases and then decreases as the conventional HEMT.The saturation phenomenon of threshold voltage degradation under high field stress verifies the existence of threshold voltage reduction effect caused by gate electron injection.
基金Project supported by the National Natural Science Foundation of China （Nos. 61404115 and 61434006）, the Program for Innovative Research Team （in Science and Technology） in University of Henan Province, China （No. 18IRTSTHN016）, and the Development Fund for Outstanding Young Teachers in Zhengzhou University, China （No. 1521317004）
文摘A two-step gate-recess process combining high selective wet-etching and non-selective digital wet-etching techniques has been proposed for InAlAs/InGaAs InP-based high electron mobility transistors （HEMTs）. High etching-selectivity ratio of InGaAs to InA1As material larger than 100 is achieved by using mixture solution of succinic acid and hydrogen peroxide （H202）. Selective wet-etching is validated in the gate-recess process of InA1As/InGaAs InP-based HEMTs, which proceeds and auto- matically stops at the InA1As barrier layer. The non-selective digital wet-etching process is developed using a separately controlled oxidation/de-oxidation technique, and during each digital etching cycle 1.2 nm InAIAs material is removed. The two-step gate-recess etching technique has been successfully incorporated into device fabrication. Digital wet-etching is repeated for two cycles with about 3 nm InAIAs barrier layer being etched off. InP-based HEMTs have demonstrated superior extrinsic trans- conductance and RF characteristics to devices fabricated during only the selective gate-recess etching process because of the smaller gate to channel distance.
基金supported by the National Key Science and Technology Special Project,China (Grant No. 2008ZX01002-002)the National Natural Science Foundation of China (Grant No. 60736033)
文摘In this paper, in order to solve the interface-trap issue and enhance the transconductance induced by high-k dielectric in metal-insulator-semiconductor （MIS） high electron mobility transistors （HEMTs）, we demonstrate better performances of recessed-gate A1203 MIS-HEMTs which are fabricated by Fluorine-based Si3N4 etching and chlorine- based A1CaN etching with three etching times （15 s, 17 s and 19 s）. The gate leakage current of MIS-HEMT is about three orders of magnitude lower than that of A1GaN/CaN HEMT. Through the recessed-gate etching, the transconductanee increases effectively. When the recessed-gate depth is 1.02 nm, the best interface performance with Tit----（0.20--1.59） p^s and Dit ：（0.55-1.08）x 1012 cm-2.eV- 1 can be obtained. After chlorine-based etching, the interface trap density reduces considerably without generating any new type of trap. The accumulated chlorine ions and the N vacancies in the AIGaN surface caused by the plasma etching can degrade the breakdown and the high frequency performances of devices. By comparing the characteristics of recessed-gate MIS-HEMTs with different etching times, it is found that a low power chlorine-based plasma etching for a short time （15 s in this paper） can enhance the performances of MIS-HEMTs effectively.
