High-Performance Organic Field-Effect Transistors Based on Two-Dimensional Vat Orange 3 Crystals

The exploration and research of low-cost,environmentally friendly,and sustainable organic semiconductor materials are of immense significance in various fields,including electronics,optoelectronics,and energy conversion.Unfortunately,these semiconductors have almost poor charge transport properties,which range from∼10^(−4) cm^(2)·V^(−1)·s^(−1) to∼10^(−2) cm^(2)·V^(−1)·s^(−1).Vat orange 3,as one of these organic semiconductors,has great potential due to its highly conjugated structure.We obtain high-quality multilayered Vat orange 3 crystals with two-dimensional(2D)growth on h-BN surfaces with thickness of 10–100 nm using physical vapor transport.Raman’s results confirm the stability of the chemical structure of Vat orange 3 during growth.Furthermore,by leveraging the structural advantages of 2D materials,an organic field-effect transistor with a 2D vdW vertical heterostructure is further realized with h-BN encapsulation and multilayered graphene contact electrodes,resulting in an excellent transistor performance with On/Off ratio of 104 and high field-effect mobility of 0.14 cm^(2)·V^(−1)·s^(−1).Our results show the great potential of Vat orange 3 with 2D structures in future nano-electronic applications.Furthermore,we showcase an approach that integrates organic semiconductors with 2D materials,aiming to offer new insights into the study of organic semiconductors.

Dynamic response of a thermal transistor to time-varying signals

Thermal transistor,the thermal analog of an electronic transistor,is one of the most important thermal devices for microscopic-scale heat manipulating.It is a three-terminal device,and the heat current flowing through two terminals can be largely controlled by the temperature of the third one.Dynamic response plays an important role in the application of electric devices and also thermal devices,which represents the devices’ability to treat fast varying inputs.In this paper,we systematically study two typical dynamic responses of a thermal transistor,i.e.,the response to a step-function input(a switching process)and the response to a square-wave input.The role of the length L of the control segment is carefully studied.It is revealed that when L is increased,the performance of the thermal transistor worsens badly.Both the relaxation time for the former process and the cutoff frequency for the latter one follow the power-law dependence on L quite well,which agrees with our analytical expectation.However,the detailed power exponents deviate from the expected values noticeably.This implies the violation of the conventional assumptions that we adopt.

Gates joint locally connected network for accurate and robust reconstruction in optical molecular tomography

Optical molecular tomography(OMT)is a potential pre-clinical molecular imaging technique with applications in a variety of biomedical areas,which can provide non-invasive quantitative three-dimensional(3D)information regarding tumor distribution in living animals.The construction of optical transmission models and the application of reconstruction algorithms in traditional model-based reconstruction processes have affected the reconstruction results,resulting in problems such as low accuracy,poor robustness,and long-time consumption.Here,a gates joint locally connected network(GLCN)method is proposed by establishing the mapping relationship between the inside source distribution and the photon density on surface directly,thus avoiding the extra time consumption caused by iteration and the reconstruction errors caused by model inaccuracy.Moreover,gates module was composed of the concatenation and multiplication operators of three different gates.It was embedded into the network aiming at remembering input surface photon density over a period and allowing the network to capture neurons connected to the true source selectively by controlling three different gates.To evaluate the performance of the proposed method,numerical simulations were conducted,whose results demonstrated good performance in terms of reconstruction positioning accuracy and robustness.

One memristor–one electrolyte-gated transistor-based high energy-efficient dropout neuronal units

Artificial neural networks(ANN) have been extensively researched due to their significant energy-saving benefits.Hardware implementations of ANN with dropout function would be able to avoid the overfitting problem. This letter reports a dropout neuronal unit(1R1T-DNU) based on one memristor–one electrolyte-gated transistor with an ultralow energy consumption of 25 p J/spike. A dropout neural network is constructed based on such a device and has been verified by MNIST dataset, demonstrating high recognition accuracies(> 90%) within a large range of dropout probabilities up to40%. The running time can be reduced by increasing dropout probability without a significant loss in accuracy. Our results indicate the great potential of introducing such 1R1T-DNUs in full-hardware neural networks to enhance energy efficiency and to solve the overfitting problem.

Effect of external magnetic field on the instability of THz plasma waves in nanoscale graphene field-effect transistors

The instability of plasma waves in the channel of field-effect transistors will cause the electromagnetic waves with THz frequency.Based on a self-consistent quantum hydrodynamic model,the instability of THz plasmas waves in the channel of graphene field-effect transistors has been investigated with external magnetic field and quantum effects.We analyzed the influence of weak magnetic fields,quantum effects,device size,and temperature on the instability of plasma waves under asymmetric boundary conditions numerically.The results show that the magnetic fields,quantum effects,and the thickness of the dielectric layer between the gate and the channel can increase the radiation frequency.Additionally,we observed that increase in temperature leads to a decrease in both oscillation frequency and instability increment.The numerical results and accompanying images obtained from our simulations provide support for the above conclusions.

11.2 W/mm power density AlGaN/GaN high electron-mobility transistors on a GaN substrate

In this letter,high power density AlGaN/GaN high electron-mobility transistors(HEMTs)on a freestanding GaN substrate are reported.An asymmetricΓ-shaped 500-nm gate with a field plate of 650 nm is introduced to improve microwave power performance.The breakdown voltage(BV)is increased to more than 200 V for the fabricated device with gate-to-source and gate-to-drain distances of 1.08 and 2.92μm.A record continuous-wave power density of 11.2 W/mm@10 GHz is realized with a drain bias of 70 V.The maximum oscillation frequency(f_(max))and unity current gain cut-off frequency(f_(t))of the AlGaN/GaN HEMTs exceed 30 and 20 GHz,respectively.The results demonstrate the potential of AlGaN/GaN HEMTs on freestanding GaN substrates for microwave power applications.

A novel enhancement mode AlGaN/GaN high electron mobility transistor with split floating gates

A novel enhancement-mode AlGaN/GaN high electron mobility transistor（HEMT） is proposed and studied.Specifically,several split floating gates（FGs） with negative charges are inserted to the conventional MIS structure.The simulation results revealed that the V_（th） decreases with the increase of polarization sheet charge density and the tunnel dielectric（between FGs and AlGaN） thickness,while it increases with the increase of FGs sheet charge density and blocking dielectric（between FGs and control gate） thickness.In the case of the same gate length,the V_（th） will left shift with decreasing FG length.More interestingly,the split FGs could significantly reduce the device failure probability in comparison with the single large area FG structure.

AlGaN/GaN high-electron-mobility transistors with transparent gates by Al-doped ZnO

AlGaN/GaN high-electron-mobility transistors （HEMTs） with Al-doped ZnO （AZO） transparent gate electrodes are fabricated, and Ni/Au/Ni-gated HEMTs are produced in comparison. The AZO-gated HEMTs show good DC characteristics and Schottky rectifying characteristics, and the gate electrodes achieve excellent transparencies. Compared with Ni/Au/Ni-gated HEMTs, AZO-gated HEMTs show a low saturation current, high threshold voltage, high Schottky barrier height, and low gate reverse leakage current. Due to the higher gate resistivity, AZO-gated HEMTs exhibit a current-gain cutoff frequency （fT） of 10 GHz and a power gain cutoff frequency （fmax） of 5 GHz, and lower maximum oscillation frequency than Ni/Au/Ni-gated HEMTs. Moreover, the C-V characteristics are measured and the gate interface characteristics of the AZO-gated devices are investigated by a C-V dual sweep.

Voltage Controlled Ring Oscillator Design with Novel 3 Transistors XNOR/XOR Gates

In present work, improved designs for voltage controlled ring oscillators (VCO) using three transistors XNOR/XOR gates have been presented. Supply voltage has been varied from [1.8 - 1.2] V in proposed designs. In first method, the VCO design using three XNOR delay cells shows frequency variation of [1.900 - 0.964] GHz with [279.429 - 16.515] μW power consumption variation. VCO designed with five XNOR delay cells shows frequency variation of [1.152 - 0.575] GHz with varying power consumption of [465.715 - 27.526] μW. In the second method VCO having three XOR stages shows frequency variation [1.9176 - 1.029] GHz with power consumption variation from [296.393 - 19.051] μW. A five stage XOR based VCO design shows frequency variation [1.049 - 0.565] GHz with power consumption variation from [493.989 - 31.753] μW. Simulations have been performed by using SPICE based on TSMC 0.18μm CMOS technology. Power consumption and output frequency range of proposed VCOs have been compared with earlier reported circuits and proposed circuit’s shows improved performance.

Atomic layer deposition for nanoscale oxide semiconductor thin film transistors:review and outlook

Since the first report of amorphous In–Ga–Zn–O based thin film transistors,interest in oxide semiconductors has grown.They offer high mobility,low off-current,low process temperature,and wide flexibility for compositions and processes.Unfortunately,depositing oxide semiconductors using conventional processes like physical vapor deposition leads to problematic issues,especially for high-resolution displays and highly integrated memory devices.Conventional approaches have limited process flexibility and poor conformality on structured surfaces.Atomic layer deposition(ALD)is an advanced technique which can provide conformal,thickness-controlled,and high-quality thin film deposition.Accordingly,studies on ALD based oxide semiconductors have dramatically increased recently.Even so,the relationships between the film properties of ALD-oxide semiconductors and the main variables associated with deposition are still poorly understood,as are many issues related to applications.In this review,to introduce ALD-oxide semiconductors,we provide:(a)a brief summary of the history and importance of ALD-based oxide semiconductors in industry,(b)a discussion of the benefits of ALD for oxide semiconductor deposition(in-situ composition control in vertical distribution/vertical structure engineering/chemical reaction and film properties/insulator and interface engineering),and(c)an explanation of the challenging issues of scaling oxide semiconductors and ALD for industrial applications.This review provides valuable perspectives for researchers who have interest in semiconductor materials and electronic device applications,and the reasons ALD is important to applications of oxide semiconductors.

Low-temperature metal–oxide thin-film transistor technologies for implementing flexible electronic circuits and systems

Here we review two 300℃metal–oxide(MO)thin-film transistor(TFT)technologies for the implementation of flexible electronic circuits and systems.Fluorination-enhanced TFTs for suppressing the variation and shift of turn-on voltage(VON),and dual-gate TFTs for acquiring sensor signals and modulating VON have been deployed to improve the robustness and performance of the systems in which they are deployed.Digital circuit building blocks based on fluorinated TFTs have been designed,fabricated,and characterized,which demonstrate the utility of the proposed low-temperature TFT technologies for implementing flexible electronic systems.The construction and characterization of an analog front-end system for the acquisition of bio-potential signals and an active-matrix sensor array for the acquisition of tactile images have been reported recently.

SiC gate-controlled bipolar field effect composite transistor with polysilicon region for improving on-state current

A novel silicon carbide gate-controlled bipolar field effect composite transistor with poly silicon region(SiC GCBTP)is proposed.Different from the traditional electrode connection mode of SiC vertical diffused MOS(VDMOS),the P+region of P-well is connected with the gate in SiC GCBTP,and the polysilicon region is added between the P+region and the gate.By this method,additional minority carriers can be injected into the drift region at on-state,and the distribution of minority carriers in the drift region will be optimized,so the on-state current is increased.In terms of static characteristics,it has the same high breakdown voltage(811 V)as SiC VDMOS whose length of drift is 5.5μm.The on-state current of SiC GCBTP is 2.47×10^(-3)A/μm(V_(G)=10 V,V_(D)=10 V)which is 5.7 times of that of SiC IGBT and 36.4 times of that of SiC VDMOS.In terms of dynamic characteristics,the turn-on time of SiC GCBTP is only 0.425 ns.And the turn-off time of SiC GCBTP is similar to that of SIC insulated gate bipolar transistor(IGBT),which is 114.72 ns.

引入上下文信息和Attention Gate的GUS-YOLO遥感目标检测算法

目前基于通用YOLO系列的遥感目标检测算法存在并未充分利用图像的全局上下文信息,在特征融合金字塔部分并未充分考虑缩小融合特征之间的语义鸿沟、抑制冗余信息干扰的缺点。在结合YOLO算法优点的基础上提出GUS-YOLO算法,其拥有一个能够充分利用全局上下文信息的骨干网络Global Backbone。除此之外,该算法在融合特征金字塔自顶向下的结构中引入Attention Gate模块,可以突出必要的特征信息,抑制冗余信息。另外,为Attention Gate模块设计了最佳的网络结构,提出了网络的特征融合结构U-Net。最后,为克服ReLU函数可能导致模型梯度不再更新的问题,该算法将Attention Gate模块的激活函数升级为可学习的SMU激活函数,提高模型鲁棒性。在NWPU VHR-10遥感数据集上,该算法相较于YOLOV7算法取得宽松指标mAP^(0.50)1.64个百分点和严格指标mAP^(0.75)9.39个百分点的性能提升。相较于目前主流的七种检测算法,该算法取得较好的检测性能。

An integrated split and dummy gates MOSFET with fast turn-off and reverse recovery characteristics

A power MOSFET with integrated split gate and dummy gate(SD-MOS) is proposed and demonstrated by the TCAD SENTAURUS.The split gate is surrounded by the source and shielded by the dummy gate.Consequently,the coupling area between the split gate and the drain electrode is reduced,thus the gate-to-drain charge(Q_(GD)),reverse transfer capacitance(C_(RSS)) and turn-off loss(E_(off)) are significantly decreased.Moreover,the MOS-channel diode is controlled by the dummy gate with ultra-thin gate oxide t_(ox),which can be turned on before the parasitic P-base/N-drift diode at the reverse conduction,then the majority carriers are injected to the N-drift to attenuate the minority injection.Therefore,the reverse recovery charge(Q_(RR)),time(T_(RR)) and peak current(I_(RRM)) are effectively reduced at the reverse freewheeling state.Additionally,the specific on-resistance(R_(on,sp)) and breakdown voltage(BV) are also studied to evaluate the static properties of the proposed SD-MOS.The simulation results show that the Q_(GD) of 6 nC/cm^(2),the C_(RSS) of 1.1 pF/cm^(2) at the V_(DS) of 150 V,the QRR of 1.2 μC/cm^(2) and the R_(on,sp) of 8.4 mΩ·cm^(2) are obtained,thus the figures of merit(FOM) including Q_(GD) ×R_(on,sp) of50 nC·mΩ,E_(off) × R_(on,sp) of 0.59 mJ·mΩ and the Q_(RR) × R_(on,sp) of 10.1 μC·mΩ are achieved for the proposed SD-MOS.

Moiré Synaptic Transistor for Homogeneous-Architecture Reservoir Computing

Reservoir computing has been considered as a promising intelligent computing paradigm for effectively processing complex temporal information.Exploiting tunable and reproducible dynamics in the single electronic device have been desired to implement the “reservoir” and the “readout” layer of reservoir computing system.Two-dimensional moiré materials,with an artificial lattice constant many times larger than the atomic length scale,are one type of most studied artificial quantum materials in community of material science and condensed-matter physics over the past years.These materials are featured with gate-tunable periodic potential and electronic correlation,thus varying the electric field allows the electrons in the moiré potential per unit cell to exhibit distinct and reproducible dynamics,showing great promise in robust reservoir computing.Here,we report that a moiré synaptic transistor can be used to implement the reservoir computing system with a homogeneous reservoir-readout architecture.The synaptic transistor is fabricated based on an h-BN/bilayer graphene/h-BN moiré heterostructure,exhibiting ferroelectricity-like hysteretic gate voltage dependence of resistance.Varying the magnitude of the gate voltage enables the moiré transistor to switch between long-term memory and shortterm memory with nonlinear dynamics.By employing the short-and long-term memories as the reservoir nodes and weights of the readout layer,respectively,we construct a full-moiré physical neural network and demonstrate that the classification accuracy of 90.8% can be achieved for the MNIST(Modified National Institute of Standards and Technology) handwritten digits database.Our work would pave the way towards the development of neuromorphic computing based on moiré materials.

Stretchable organic electrochemical transistors with micro-/nano-structures

Organic electrochemical transistors(OECTs)have attracted attention due to their unique function of converting ionic and biological signals into electronic signals,high transconductance,low energy consumption(below 1 V),stable operation in aqueous media,good biocompatibility[1,2].However,most OECTs are usually built on brittle and stiff substrates,and inappropriate to be adhered to or contacted with delicate human skin,thus impeding their use in wearable electronics.It is desirable to exploit stretchable OECTs to reduce the mechanical mismatch with soft tissues.

Skyrmion-based logic gates controlled by electric currents in synthetic antiferromagnet

Skyrmions in synthetic antiferromagnetic(SAF) systems have attracted much attention in recent years due to their superior stability, high-speed mobility, and completely compensated skyrmion Hall effect. They are promising building blocks for the next generation of magnetic storage and computing devices with ultra-low energy and ultra-high density.Here, we theoretically investigate the motion of a skyrmion in an SAF bilayer racetrack and find the velocity of a skyrmion can be controlled jointly by the edge effect and the driving force induced by the spin current. Furthermore, we propose a logic gate that can realize different logic functions of logic AND, OR, NOT, NAND, NOR, and XOR gates. Several effects including the spin–orbit torque, the skyrmion Hall effect, skyrmion–skyrmion repulsion, and skyrmion–edge interaction are considered in this design. Our work may provide a way to utilize the SAF skyrmion as a versatile information carrier for future energy-efficient logic gates.

P-type cold-source field-effect transistors with TcX_(2) and ReX_(2)(X=S,Se)cold source electrodes:A computational study

Cold-source field-effect transistors(CS-FETs)have been developed to overcome the major challenge of power dissipation in modern integrated circuits.Cold metals suitable for n-type CS-FETs have been proposed as the ideal electrode to filter the high-energy electrons and break the thermal limit on subthreshold swing(SS).In this work,regarding the p-type CS-FETs,we propose TcX_(2) and ReX_(2)(X=S,Se)as the injection source to realize the sub-thermal switching for holes.First-principles calculations unveils the cold-metal characteristics of monolayer TcX_(2) and ReX_(2),possessing a sub-gap below the Fermi level and a decreasing DOS with energy.Quantum device simulations demonstrate that TcX_(2) and ReX_(2) can enable the cold source effects in WSe_(2) p-type FETs,achieving steep SS of 29-38 mV/dec and high on/off ratios of(2.3-5.6)×10^(7).Moreover,multilayer Re S2retains the cold metal characteristic,thus ensuring similar CS-FET performances to that of the monolayer source.This work underlines the significance of cold metals for the design of p-type CS-FETs.

Charge trapping effect at the interface of ferroelectric/interlayer in the ferroelectric field effect transistor gate stack

We study the charge trapping phenomenon that restricts the endurance of n-type ferroelectric field-effect transistors(FeFETs)with metal/ferroelectric/interlayer/Si(MFIS)gate stack structure.In order to explore the physical mechanism of the endurance failure caused by the charge trapping effect,we first establish a model to simulate the electron trapping behavior in n-type Si FeFET.The model is based on the quantum mechanical electron tunneling theory.And then,we use the pulsed I_d-V_g method to measure the threshold voltage shift between the rising edges and falling edges of the FeFET.Our model fits the experimental data well.By fitting the model with the experimental data,we get the following conclusions.(i)During the positive operation pulse,electrons in the Si substrate are mainly trapped at the interface between the ferroelectric(FE)layer and interlayer(IL)of the FeFET gate stack by inelastic trap-assisted tunneling.(ii)Based on our model,we can get the number of electrons trapped into the gate stack during the positive operation pulse.(iii)The model can be used to evaluate trap parameters,which will help us to further understand the fatigue mechanism of FeFET.

Homojunction structure amorphous oxide thin film transistors with ultra-high mobility

Amorphous oxide semiconductors(AOS)have unique advantages in transparent and flexible thin film transistors(TFTs)applications,compared to low-temperature polycrystalline-Si(LTPS).However,intrinsic AOS TFTs are difficult to obtain field-effect mobility(μFE)higher than LTPS(100 cm^(2)/(V·s)).Here,we design ZnAlSnO(ZATO)homojunction structure TFTs to obtainμFE=113.8 cm^(2)/(V·s).The device demonstrates optimized comprehensive electrical properties with an off-current of about1.5×10^(-11)A,a threshold voltage of–1.71 V,and a subthreshold swing of 0.372 V/dec.There are two kinds of gradient coupled in the homojunction active layer,which are micro-crystallization and carrier suppressor concentration gradient distribution so that the device can reduce off-current and shift the threshold voltage positively while maintaining high field-effect mobility.Our research in the homojunction active layer points to a promising direction for obtaining excellent-performance AOS TFTs.