Purification is a primary application of zone melting, in which the improvement of efficiency, production yield and minimum achievable impurity level are always the research focus due to the increasing demand for high...Purification is a primary application of zone melting, in which the improvement of efficiency, production yield and minimum achievable impurity level are always the research focus due to the increasing demand for high purity metals. This paper has systematically outlined the whole development of related research on zone refining of metals including basic theories, variants of zone refining, parametric optimization, numerical models, and high purity analytical methods. The collection of this information could be of good value to improve the refining efficiency and the production of high purity metals by zone refining.展开更多
High-performance Ge n~＋/p junctions were fabricated at a low formation temperature from 325℃ to 400℃ with a metal（nickel）-induced dopant activation technique. The obtained Ni Ge electroded Ge n＋/p junction has a...High-performance Ge n~＋/p junctions were fabricated at a low formation temperature from 325℃ to 400℃ with a metal（nickel）-induced dopant activation technique. The obtained Ni Ge electroded Ge n＋/p junction has a rectification ratio of 5.6×10~4 and a forward current of 387 A/cm^2at -1 V bias. The Ni-based metal-induced dopant activation technique is expected to meet the requirement of the shallow junction of Ge MOSFET.展开更多
An extensive and complete experimental investigation with a full layout design of the channel direction was carried out for the first time to clarify the orientation dependence of germanium p-channel metal-oxide-semic...An extensive and complete experimental investigation with a full layout design of the channel direction was carried out for the first time to clarify the orientation dependence of germanium p-channel metal-oxide-semiconductor field-effect transistors （PMOSFETs）. By comparison of gate trans-conductance, drive current, and hole mobility, we found that the performance trend with the substrate orientation for Ge PMOSFET is （110）〉（111） ~ （100）, and the best channel direction is （110）/[110]. Moreover, the （110） device performance was found to be easily degraded as the channel direction got off from the [ 110] orientation, while （100） and （111） devices exhibited less channel orientation dependence. This experimental result shows good matching with the simulation reports to give a credible and significant guidance for Ge PMOSFET design.展开更多
Wet thermal annealing effects on the properties of TaN/HfO2/Ge metal-oxide-semiconductor （MOS） structures with and without a GeO2 passivation layer are investigated. The physical and the electrical properties are ch...Wet thermal annealing effects on the properties of TaN/HfO2/Ge metal-oxide-semiconductor （MOS） structures with and without a GeO2 passivation layer are investigated. The physical and the electrical properties are characterized by X-ray photoemission spectroscopy, high-resolution transmission electron microscopy, capacitance-voltage （C-V） and current-voltage characteristics. It is demonstrated that wet thermal annealing at relatively higher temperature such as 550 ℃ can lead to Ge incorporation in HfO2 and the partial crystallization of HfO2, which should be responsible for the serious degradation of the electrical characteristics of the TaN/HfO2/Ge MOS capacitors. However, wet thermal annealing at 400 ℃ can decrease the GeOx interlayer thickness at the HfO2/Ge interface, resulting in a significant reduction of the interface states and a smaller effective oxide thickness, along with the introduction of a positive charge in the dielectrics due to the hydrolyzable property of GeOx in the wet ambient. The pre-growth of a thin GeO2 passivation layer can effectively suppress the interface states and improve the C V characteristics for the as-prepared HfO2 gated Ge MOS capacitors, but it also dissembles the benefits of wet thermal annealing to a certain extent.展开更多
通过理论计算,对比分析了不同界面层对金属与n型锗(Ge)接触的影响。结果表明,界面层有利于降低费米能级钉扎效应,使金属与n型Ge接触的电子势垒高度降低。然而,由于界面层与Ge的导带之间存在带阶,界面层额外增加了不利的隧穿电阻。优化...通过理论计算,对比分析了不同界面层对金属与n型锗(Ge)接触的影响。结果表明,界面层有利于降低费米能级钉扎效应,使金属与n型Ge接触的电子势垒高度降低。然而,由于界面层与Ge的导带之间存在带阶,界面层额外增加了不利的隧穿电阻。优化选择合适的界面层材料,降低电子势垒高度的同时减小隧穿电阻,有利于减小比接触电阻率。采用厚度为1.5 nm的Zn O作界面层,电子势垒高度为0.075 e V,比接触电阻率为2×10-8Ω·cm2,比无界面层的0.26Ω·cm2降低了7个数量级。展开更多
随着超大规模集成电路技术的发展,CMOS器件的制备过程需要同时引入金属栅和超浅结等新的先进工艺技术,因此各种新工艺的兼容性研究具有重要意义.本文研究了超浅结工艺中使用的锗预非晶化对镍硅(N iS i)金属栅功函数的影响.对具有不同剂...随着超大规模集成电路技术的发展,CMOS器件的制备过程需要同时引入金属栅和超浅结等新的先进工艺技术,因此各种新工艺的兼容性研究具有重要意义.本文研究了超浅结工艺中使用的锗预非晶化对镍硅(N iS i)金属栅功函数的影响.对具有不同剂量Ge注入的N iS i金属栅MOS电容样品的研究表明,锗预非晶化采用的Ge注入对N iS i金属栅的功函数影响很小(小于0.03eV),而且Ge注入也不会导致氧化层中固定电荷以及氧化层和硅衬底之间界面态的增加.这些结果表明,在自对准的先进CMOS工艺中,N iS i金属栅工艺和锗预非晶化超浅结工艺可以互相兼容.展开更多
文摘Purification is a primary application of zone melting, in which the improvement of efficiency, production yield and minimum achievable impurity level are always the research focus due to the increasing demand for high purity metals. This paper has systematically outlined the whole development of related research on zone refining of metals including basic theories, variants of zone refining, parametric optimization, numerical models, and high purity analytical methods. The collection of this information could be of good value to improve the refining efficiency and the production of high purity metals by zone refining.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.61176092 and 61474094)the National Natural Science Foundation of China–National Research Foundation of Korea Joint Research Project(Grant No.11311140251)the National Basic Research Program of China(Grant Nos.2012CB933503 and 2013CB632103)
文摘High-performance Ge n~＋/p junctions were fabricated at a low formation temperature from 325℃ to 400℃ with a metal（nickel）-induced dopant activation technique. The obtained Ni Ge electroded Ge n＋/p junction has a rectification ratio of 5.6×10~4 and a forward current of 387 A/cm^2at -1 V bias. The Ni-based metal-induced dopant activation technique is expected to meet the requirement of the shallow junction of Ge MOSFET.
基金supported by the National Basic Research Program of China(Grant No.2011CBA00601)the National Science and Technology Major Project of the Ministry of Science and Technology of China(Grant No.2009ZX02035-001)the National Natural Science Foundation of China(Grant Nos.60625403,60806033,and 60925015)
文摘An extensive and complete experimental investigation with a full layout design of the channel direction was carried out for the first time to clarify the orientation dependence of germanium p-channel metal-oxide-semiconductor field-effect transistors （PMOSFETs）. By comparison of gate trans-conductance, drive current, and hole mobility, we found that the performance trend with the substrate orientation for Ge PMOSFET is （110）〉（111） ~ （100）, and the best channel direction is （110）/[110]. Moreover, the （110） device performance was found to be easily degraded as the channel direction got off from the [ 110] orientation, while （100） and （111） devices exhibited less channel orientation dependence. This experimental result shows good matching with the simulation reports to give a credible and significant guidance for Ge PMOSFET design.
基金Project supported by the National Natural Science Foundation of China (Grant Nos. 61176092,61036003,and 60837001)the National Basic Research Program of China (Grant No. 2012CB933503)+1 种基金the Ph.D. Program Foundation of Ministry of Education of China (Grant No. 20110121110025)the Fundamental Research Funds for the Central Universities,China (Grant No. 2010121056)
文摘Wet thermal annealing effects on the properties of TaN/HfO2/Ge metal-oxide-semiconductor （MOS） structures with and without a GeO2 passivation layer are investigated. The physical and the electrical properties are characterized by X-ray photoemission spectroscopy, high-resolution transmission electron microscopy, capacitance-voltage （C-V） and current-voltage characteristics. It is demonstrated that wet thermal annealing at relatively higher temperature such as 550 ℃ can lead to Ge incorporation in HfO2 and the partial crystallization of HfO2, which should be responsible for the serious degradation of the electrical characteristics of the TaN/HfO2/Ge MOS capacitors. However, wet thermal annealing at 400 ℃ can decrease the GeOx interlayer thickness at the HfO2/Ge interface, resulting in a significant reduction of the interface states and a smaller effective oxide thickness, along with the introduction of a positive charge in the dielectrics due to the hydrolyzable property of GeOx in the wet ambient. The pre-growth of a thin GeO2 passivation layer can effectively suppress the interface states and improve the C V characteristics for the as-prepared HfO2 gated Ge MOS capacitors, but it also dissembles the benefits of wet thermal annealing to a certain extent.
文摘通过理论计算,对比分析了不同界面层对金属与n型锗(Ge)接触的影响。结果表明,界面层有利于降低费米能级钉扎效应,使金属与n型Ge接触的电子势垒高度降低。然而,由于界面层与Ge的导带之间存在带阶,界面层额外增加了不利的隧穿电阻。优化选择合适的界面层材料,降低电子势垒高度的同时减小隧穿电阻,有利于减小比接触电阻率。采用厚度为1.5 nm的Zn O作界面层,电子势垒高度为0.075 e V,比接触电阻率为2×10-8Ω·cm2,比无界面层的0.26Ω·cm2降低了7个数量级。
文摘随着超大规模集成电路技术的发展,CMOS器件的制备过程需要同时引入金属栅和超浅结等新的先进工艺技术,因此各种新工艺的兼容性研究具有重要意义.本文研究了超浅结工艺中使用的锗预非晶化对镍硅(N iS i)金属栅功函数的影响.对具有不同剂量Ge注入的N iS i金属栅MOS电容样品的研究表明,锗预非晶化采用的Ge注入对N iS i金属栅的功函数影响很小(小于0.03eV),而且Ge注入也不会导致氧化层中固定电荷以及氧化层和硅衬底之间界面态的增加.这些结果表明,在自对准的先进CMOS工艺中,N iS i金属栅工艺和锗预非晶化超浅结工艺可以互相兼容.
