The Godson-2G microprocessor is a high performance SOC which integrates a four-issue 64-bit high performance CPU core （called GS464）, a DDR2/3 controller, a HyperTransport controller, a PCI/PCI-X controller, etc. It...The Godson-2G microprocessor is a high performance SOC which integrates a four-issue 64-bit high performance CPU core （called GS464）, a DDR2/3 controller, a HyperTransport controller, a PCI/PCI-X controller, etc. It is physically implemented in 65 nm CMOS process and reaches the frequency of 1GHz with power consumption less than 4 W. The main challenges of Godson-2G physical implementation include nanometer process technology effects, high performance design targets, and tight schedule. This paper describes the key innovative features of physical design methodology which had been used in Godson-2G physical implementation, with particular emphasis on interconnect driven floorplan generation （ICD-FP）, adapted boundary constraints design optimization （ABC-OPT）, automatic register group clock tree generation methodology （ARG-CTS）.展开更多
Multithreaded technique is the developing trend of high performance processor. Memory consistency model is essential to the correctness, performance and complexity of multithreaded processor. The chip multithreaded co...Multithreaded technique is the developing trend of high performance processor. Memory consistency model is essential to the correctness, performance and complexity of multithreaded processor. The chip multithreaded consistency model adapting to multithreaded processor is proposed in this paper. The restriction imposed on memory event ordering by chip multithreaded consistency is presented and formalized. With the idea of critical cycle built by Wei-Wu Hu, we prove that the proposed chip multithreaded consistency model satisfies the criterion of correct execution of sequential consistency model. Chip multithreaded consistency model provides a way of achieving high performance compared with sequential consistency model and easures the compatibility of software that the execution result in multithreaded processor is the same as the execution result in uniprocessor. The implementation strategy of chip multithreaded consistency model in Godson-2 SMT processor is also proposed. Godson-2 SMT processor supports chip multithreaded consistency model correctly by exception scheme based on the sequential memory access queue of each thread.展开更多
基金Supported by the National High Technology Research and Development 863 Program of China under Grant No.2007AA01Z114.
文摘The Godson-2G microprocessor is a high performance SOC which integrates a four-issue 64-bit high performance CPU core （called GS464）, a DDR2/3 controller, a HyperTransport controller, a PCI/PCI-X controller, etc. It is physically implemented in 65 nm CMOS process and reaches the frequency of 1GHz with power consumption less than 4 W. The main challenges of Godson-2G physical implementation include nanometer process technology effects, high performance design targets, and tight schedule. This paper describes the key innovative features of physical design methodology which had been used in Godson-2G physical implementation, with particular emphasis on interconnect driven floorplan generation （ICD-FP）, adapted boundary constraints design optimization （ABC-OPT）, automatic register group clock tree generation methodology （ARG-CTS）.
基金Supported by the National High Technology Development 863 Program of China(Grant Nos.2007AA01Z114, 2006AA010201)the National Natural Science Foundation of China(Grant Nos.60703017, 60736012, 60325205, 60673146, 60603049)+1 种基金the National Grand Fundamental Research 973 Program of China(Grant Nos.2005CB321601, 2005CB321603)Beijing Natural Science Foundation(Grant No.4072024).
文摘Multithreaded technique is the developing trend of high performance processor. Memory consistency model is essential to the correctness, performance and complexity of multithreaded processor. The chip multithreaded consistency model adapting to multithreaded processor is proposed in this paper. The restriction imposed on memory event ordering by chip multithreaded consistency is presented and formalized. With the idea of critical cycle built by Wei-Wu Hu, we prove that the proposed chip multithreaded consistency model satisfies the criterion of correct execution of sequential consistency model. Chip multithreaded consistency model provides a way of achieving high performance compared with sequential consistency model and easures the compatibility of software that the execution result in multithreaded processor is the same as the execution result in uniprocessor. The implementation strategy of chip multithreaded consistency model in Godson-2 SMT processor is also proposed. Godson-2 SMT processor supports chip multithreaded consistency model correctly by exception scheme based on the sequential memory access queue of each thread.
