Grain coalescence has been applied in many areas of nanofabrication technology, including modification of thinfilm properties, nanowelding, and self-assembly of nanostructures. However, very few systematic studies of ...Grain coalescence has been applied in many areas of nanofabrication technology, including modification of thinfilm properties, nanowelding, and self-assembly of nanostructures. However, very few systematic studies of selfassembly using the grain coalescence, especially for threedimensional(3D) nanostructures, exist at present. Here, we investigate the mechanism of plasma triggered grain coalescence to achieve the precise control of nanoscale phase and morphology of the grain coalescence induced by exothermic energy. Exothermic energy is generated through etching a silicon substrate via application of plasma. By tuning the plasma power and the flow rates of reactive gases, different etching rates and profiles can be achieved, resulting in various morphologies of grain coalescence. Balancing the isotropic/anisotropic substrate etching profile and the etching rate makes it possible to simultaneously release 2D nanostructures from the substrate and induce enough surface tension force,generated by grain coalescence, to form 3D nanostructures.Diverse morphologies of 3D nanostructures have been obtained by the grain coalescence, and a strategy to achieve self-assembly, resulting in desired 3D nanostructures, has been proposed and demonstrated.展开更多
Declarative Programming Languages (DPLs) apply a process model of Horn claun es such as PARLOG[8] or a reduction model of A-calculus such as SML[7] and are) in principle, well suited to multiprocessor implemelltation....Declarative Programming Languages (DPLs) apply a process model of Horn claun es such as PARLOG[8] or a reduction model of A-calculus such as SML[7] and are) in principle, well suited to multiprocessor implemelltation. However, the performance of a parallel declarative program can be impaired by a mismatch between the parallelism available in an application and the parallelism available in the architecture. A particularly attractive solution is to automatically match the parallelism of the program to the parallelism of the target hardware as a compilation step. In this paper) we present an optimizillg compilation technique called granularity analysis which identi fies and removes excess parallelism that would degrade performance. The main steps are: an analysis of the flow of data to form an attributed call graph between function (or predicate) arguments; and an asymptotic estimation of granularity of a function (or predicate) to generate approximate grain size. Compiled procedure calls can be annotated with grain size and a task scheduler can make scheduling decisions with the classilication scheme of grains to control parallelism at runtime. The resulting granularity analysis scheme is suitable for exploiting adaptive parallelism of declarative programming languages on multiprocessors.展开更多
基金supported by an NSF CAREER Award(CMMI-1454293)a Grant-In-Aid(GIA)program/a start-up fund at the University of Minnesota,Twin Cities+2 种基金Parts of this work were carried out in the Characterization Facility,University of Minnesota,a member of the NSF-funded Materials Research Facilities Network(www.mrfn.org)via the MRSEC programA portion of this work was also carried out in the Minnesota Nano Center which receives partial support from the NSF through the NNCI programthe 3M Science and Technology Fellowship
文摘Grain coalescence has been applied in many areas of nanofabrication technology, including modification of thinfilm properties, nanowelding, and self-assembly of nanostructures. However, very few systematic studies of selfassembly using the grain coalescence, especially for threedimensional(3D) nanostructures, exist at present. Here, we investigate the mechanism of plasma triggered grain coalescence to achieve the precise control of nanoscale phase and morphology of the grain coalescence induced by exothermic energy. Exothermic energy is generated through etching a silicon substrate via application of plasma. By tuning the plasma power and the flow rates of reactive gases, different etching rates and profiles can be achieved, resulting in various morphologies of grain coalescence. Balancing the isotropic/anisotropic substrate etching profile and the etching rate makes it possible to simultaneously release 2D nanostructures from the substrate and induce enough surface tension force,generated by grain coalescence, to form 3D nanostructures.Diverse morphologies of 3D nanostructures have been obtained by the grain coalescence, and a strategy to achieve self-assembly, resulting in desired 3D nanostructures, has been proposed and demonstrated.
文摘Declarative Programming Languages (DPLs) apply a process model of Horn claun es such as PARLOG[8] or a reduction model of A-calculus such as SML[7] and are) in principle, well suited to multiprocessor implemelltation. However, the performance of a parallel declarative program can be impaired by a mismatch between the parallelism available in an application and the parallelism available in the architecture. A particularly attractive solution is to automatically match the parallelism of the program to the parallelism of the target hardware as a compilation step. In this paper) we present an optimizillg compilation technique called granularity analysis which identi fies and removes excess parallelism that would degrade performance. The main steps are: an analysis of the flow of data to form an attributed call graph between function (or predicate) arguments; and an asymptotic estimation of granularity of a function (or predicate) to generate approximate grain size. Compiled procedure calls can be annotated with grain size and a task scheduler can make scheduling decisions with the classilication scheme of grains to control parallelism at runtime. The resulting granularity analysis scheme is suitable for exploiting adaptive parallelism of declarative programming languages on multiprocessors.
