In order to increase the hardware utilization and minimize the chip area a multi-transform coding architecture which includes 4 ×4 forward integer transform 4 ×4 inverse integer transform 4 ×4 Hadamard ...In order to increase the hardware utilization and minimize the chip area a multi-transform coding architecture which includes 4 ×4 forward integer transform 4 ×4 inverse integer transform 4 ×4 Hadamard transform and 2 ×2 Hadamard transform is proposed. By simplifying these transforms and exploring their similarities the proposed design merges the architectures processing individual transforms into a high-performance multi-transform coding architecture.Using a semiconductor manufacturing international corporation SMIC 0.18 μm complementary metal oxide semiconductor CMOS technology the proposed architecture achieves the maximum operating clock frequency of 200 MHz and the throughput rate of 800 ×106 pixel/s with the hardware cost of 3 704 gates.The results demonstrate that the data throughput rate per unit area DTUA of this design is at least 40.28%higher than that of the reference design.This design can meet the requirements of real-time decoding digital cinema video 4 096 ×2 048@30 Hz at 62.9 MHz which helps to reduce the power consumption.展开更多
The dilemma of the quantization parameter (QP) being involved in both rate control and rate-distortion optimization (RDO) prevents using the traditional rate control scheme. Although some rate control schemes are prop...The dilemma of the quantization parameter (QP) being involved in both rate control and rate-distortion optimization (RDO) prevents using the traditional rate control scheme. Although some rate control schemes are proposed to circumvent the dilemma, the inaccurate prediction model and improper bit allocation deter H.264 application on low bandwidth channel. To resolve this issue, this paper proposes a novel rate control scheme by considering the macroblock (MB) encoding complexity variation and buffer variation and by exploiting the spatio-temporal correlation sufficiently well. Simulations showed that this scheme improves the perceptual quality of the pictures with similar or smaller PSNR deviations when compared to that of rate control in JVT-O016.展开更多
This letter proposes a rate control algorithm for H.264 video encoder, which is based on block activity and buffer state. Experimental results indicate that it has an excellent performance by providing much accurate b...This letter proposes a rate control algorithm for H.264 video encoder, which is based on block activity and buffer state. Experimental results indicate that it has an excellent performance by providing much accurate bit rate and better coding efficiency compared with H.264. The computational complexity of the algorithm is reduced by adopting a novel block activity description method using the Sum of Absolute Difference (SAD) of 16× 16 mode, and its robustness is enhanced by introducing a feedback circuit at frame layer.展开更多
基金The National Key Technology R&D Program of China during the 12th Five Year Plan Period(No.2013BAJ05B03)
文摘In order to increase the hardware utilization and minimize the chip area a multi-transform coding architecture which includes 4 ×4 forward integer transform 4 ×4 inverse integer transform 4 ×4 Hadamard transform and 2 ×2 Hadamard transform is proposed. By simplifying these transforms and exploring their similarities the proposed design merges the architectures processing individual transforms into a high-performance multi-transform coding architecture.Using a semiconductor manufacturing international corporation SMIC 0.18 μm complementary metal oxide semiconductor CMOS technology the proposed architecture achieves the maximum operating clock frequency of 200 MHz and the throughput rate of 800 ×106 pixel/s with the hardware cost of 3 704 gates.The results demonstrate that the data throughput rate per unit area DTUA of this design is at least 40.28%higher than that of the reference design.This design can meet the requirements of real-time decoding digital cinema video 4 096 ×2 048@30 Hz at 62.9 MHz which helps to reduce the power consumption.
文摘The dilemma of the quantization parameter (QP) being involved in both rate control and rate-distortion optimization (RDO) prevents using the traditional rate control scheme. Although some rate control schemes are proposed to circumvent the dilemma, the inaccurate prediction model and improper bit allocation deter H.264 application on low bandwidth channel. To resolve this issue, this paper proposes a novel rate control scheme by considering the macroblock (MB) encoding complexity variation and buffer variation and by exploiting the spatio-temporal correlation sufficiently well. Simulations showed that this scheme improves the perceptual quality of the pictures with similar or smaller PSNR deviations when compared to that of rate control in JVT-O016.
基金the National Nature Science Foundation of China(No.90104013) 863 Project(No.2002AA119010, 2001AA121061 and 2002AA123041)
文摘This letter proposes a rate control algorithm for H.264 video encoder, which is based on block activity and buffer state. Experimental results indicate that it has an excellent performance by providing much accurate bit rate and better coding efficiency compared with H.264. The computational complexity of the algorithm is reduced by adopting a novel block activity description method using the Sum of Absolute Difference (SAD) of 16× 16 mode, and its robustness is enhanced by introducing a feedback circuit at frame layer.
