Given the substantially increasing complexity of embedded systems, the use of relatively detailed clock cycle-accurate simulators for the design-space exploration is impractical in the early design stages. Raising the...Given the substantially increasing complexity of embedded systems, the use of relatively detailed clock cycle-accurate simulators for the design-space exploration is impractical in the early design stages. Raising the abstraction level is nowadays widely seen as a solution to bridge the gap between the increasing system complexity and the low design productivity. For this, several system-level design tools and methodologies have been introduced to efficiently explore the design space of heterogeneous signal processing systems. In this paper, we demonstrate the effectiveness and the flexibility of the Sesame/Artemis system-level modeling and simulation methodology for efficient peformance evaluation and rapid architectural exploration of the increasing complexity heterogeneous embedded media systems. For this purpose, we have selected a system level design of a very high complexity media application;a H.264/AVC (Advanced Video Codec) video encoder. The encoding performances will be evaluated using system-level simulations targeting multiple heterogeneous multiprocessors platforms.展开更多
This paper presents a hardware efficient high definition television (HDTV) encoder for H.264/AVC. We use a two-level mode decision (MD) mechanism to reduce the complexity and maintain the performance, and design a sha...This paper presents a hardware efficient high definition television (HDTV) encoder for H.264/AVC. We use a two-level mode decision (MD) mechanism to reduce the complexity and maintain the performance, and design a sharable architecture for normal mode fractional motion estimation (NFME), special mode fractional motion estimation (SFME), and luma motion compensation (LMC), to decrease the hardware cost. Based on these technologies, we adopt a four-stage macro-block pipeline scheme using an efficient memory management strategy for the system, which greatly reduces on-chip memory and bandwidth requirements. The proposed encoder uses about 1126k gates with an average Bjontegaard-Delta peak signal-to-noise ratio (BD-PSNR) decrease of 0.5 dB, compared with JM15.0. It can fully satisfy the real-time video encoding for 1080p@30 frames/s of H.264/AVC high profile.展开更多
The H.264/AVC video coding standard uses an intra prediction mode with 4×4 and 16×16 blocks for luma and 8×8 blocks for chroma. This standard uses the rate distortion optimization (RDO) method to determ...The H.264/AVC video coding standard uses an intra prediction mode with 4×4 and 16×16 blocks for luma and 8×8 blocks for chroma. This standard uses the rate distortion optimization (RDO) method to determine the best coding mode based on the compression performance and video quality. This method offers a large improvement in coding efficiency compared to other compression standards, but the computational complexity is greater due to the various intra prediction modes. This paper proposes a fast intra mode decision algorithm for real-time encoding of H.264/AVC based on the dominant edge direction (DED). The DED is extracted using pixel value summation and subtraction in the horizontal and vertical directions. By using the DED, three modes instead of nine are chosen for RDO calculation to decide on the best mode in the 4×4 luma block. For the 16×16 luma and the 8×8 chroma, only two modes are chosen instead of four. Experimental results show that the entire encoding time saving of the proposed algorithm is about 67% compared to the full intra search method with negligible loss of quality.展开更多
Image sequences processing and video encoding are extremely time consuming problems. The time complexity of them depends on image contents. This paper presents an estimation of a block motion method for video coding w...Image sequences processing and video encoding are extremely time consuming problems. The time complexity of them depends on image contents. This paper presents an estimation of a block motion method for video coding with edge alignment. This method uses blocks of size 4 × 4 and its basic idea is to find motion vector using the edge position in each video coding block. The method finds the motion vectors more accurately and faster than any known classical method that calculates all the possibilities. Our presented algorithm is compared with known classical algorithms using the evaluation function of the peak signal-to-noise ratio. For comparison of the methods we are using parameters such as time, CPU usage, and size of compressed data. The comparison is made on benchmark data in color format YUV. Results of our proposed method are comparable and in some cases better than results of standard classical algorithms.展开更多
作为视频通信中非常重要的关键技术之一,码率控制用于调整视频码流以满足带宽受限的条件,能够直接影响视频编码器输出码率的稳定性和保证视频质量。首先描述码率控制问题,给出码率控制算法的分类准则;然后对众多的H.264/先进视频编码(ad...作为视频通信中非常重要的关键技术之一,码率控制用于调整视频码流以满足带宽受限的条件,能够直接影响视频编码器输出码率的稳定性和保证视频质量。首先描述码率控制问题,给出码率控制算法的分类准则;然后对众多的H.264/先进视频编码(advanced video coding,AVC)码率控制算法根据应用目的进行具体描述;最后从适用标准和应用目的两个方面,详细指出码率控制技术今后的研究方向。展开更多
文摘Given the substantially increasing complexity of embedded systems, the use of relatively detailed clock cycle-accurate simulators for the design-space exploration is impractical in the early design stages. Raising the abstraction level is nowadays widely seen as a solution to bridge the gap between the increasing system complexity and the low design productivity. For this, several system-level design tools and methodologies have been introduced to efficiently explore the design space of heterogeneous signal processing systems. In this paper, we demonstrate the effectiveness and the flexibility of the Sesame/Artemis system-level modeling and simulation methodology for efficient peformance evaluation and rapid architectural exploration of the increasing complexity heterogeneous embedded media systems. For this purpose, we have selected a system level design of a very high complexity media application;a H.264/AVC (Advanced Video Codec) video encoder. The encoding performances will be evaluated using system-level simulations targeting multiple heterogeneous multiprocessors platforms.
基金supported by the National Natural Science Foundation of China (No. 61076021)the Program for New Century Excellent Talents in Universities, China
文摘This paper presents a hardware efficient high definition television (HDTV) encoder for H.264/AVC. We use a two-level mode decision (MD) mechanism to reduce the complexity and maintain the performance, and design a sharable architecture for normal mode fractional motion estimation (NFME), special mode fractional motion estimation (SFME), and luma motion compensation (LMC), to decrease the hardware cost. Based on these technologies, we adopt a four-stage macro-block pipeline scheme using an efficient memory management strategy for the system, which greatly reduces on-chip memory and bandwidth requirements. The proposed encoder uses about 1126k gates with an average Bjontegaard-Delta peak signal-to-noise ratio (BD-PSNR) decrease of 0.5 dB, compared with JM15.0. It can fully satisfy the real-time video encoding for 1080p@30 frames/s of H.264/AVC high profile.
基金Project (No. IITA-2009-(C1090-0902-0011)) supported by the Ministry of Knowledge Economy of Korea under the ITRC Support Program supervised by the IITA
文摘The H.264/AVC video coding standard uses an intra prediction mode with 4×4 and 16×16 blocks for luma and 8×8 blocks for chroma. This standard uses the rate distortion optimization (RDO) method to determine the best coding mode based on the compression performance and video quality. This method offers a large improvement in coding efficiency compared to other compression standards, but the computational complexity is greater due to the various intra prediction modes. This paper proposes a fast intra mode decision algorithm for real-time encoding of H.264/AVC based on the dominant edge direction (DED). The DED is extracted using pixel value summation and subtraction in the horizontal and vertical directions. By using the DED, three modes instead of nine are chosen for RDO calculation to decide on the best mode in the 4×4 luma block. For the 16×16 luma and the 8×8 chroma, only two modes are chosen instead of four. Experimental results show that the entire encoding time saving of the proposed algorithm is about 67% compared to the full intra search method with negligible loss of quality.
文摘Image sequences processing and video encoding are extremely time consuming problems. The time complexity of them depends on image contents. This paper presents an estimation of a block motion method for video coding with edge alignment. This method uses blocks of size 4 × 4 and its basic idea is to find motion vector using the edge position in each video coding block. The method finds the motion vectors more accurately and faster than any known classical method that calculates all the possibilities. Our presented algorithm is compared with known classical algorithms using the evaluation function of the peak signal-to-noise ratio. For comparison of the methods we are using parameters such as time, CPU usage, and size of compressed data. The comparison is made on benchmark data in color format YUV. Results of our proposed method are comparable and in some cases better than results of standard classical algorithms.
文摘作为视频通信中非常重要的关键技术之一,码率控制用于调整视频码流以满足带宽受限的条件,能够直接影响视频编码器输出码率的稳定性和保证视频质量。首先描述码率控制问题,给出码率控制算法的分类准则;然后对众多的H.264/先进视频编码(advanced video coding,AVC)码率控制算法根据应用目的进行具体描述;最后从适用标准和应用目的两个方面,详细指出码率控制技术今后的研究方向。
