In this article, a design for the adaptive deblocking filter is proposed. To understand the real-time performance, a FILTER unit that can process eight pixels beside an edge simultaneously is applied in this design to...In this article, a design for the adaptive deblocking filter is proposed. To understand the real-time performance, a FILTER unit that can process eight pixels beside an edge simultaneously is applied in this design to increase filtering efficiency, and local memory is used to store all temporary data generated by the FILTER to reduce access to system bus. The filter makes every 4×4 sample block pipelined through the process units and achieves an efficiency of 80% for both the FILTER unit and the bus access unit. It can fulfill filtering process for a crystallographic information file （CIF, 352×288） format picture in 95 k clock cycles. The proposed design is part of a H.264/AVC decoder system-on-chip （SOC）, which is fabricated in 0.18 μm complementary metal oxide semiconductor （CMOS） process. The filter module consists of 60 k gates and 25.7 kb static random access memory （SRAM） and it can filter a macro-block in 240 clock cycles.展开更多
基金supported by the National Natural Science Foundation of China (60372021)the Hi-Tech Research and Development Program of China (2003AA1Z1100).
文摘In this article, a design for the adaptive deblocking filter is proposed. To understand the real-time performance, a FILTER unit that can process eight pixels beside an edge simultaneously is applied in this design to increase filtering efficiency, and local memory is used to store all temporary data generated by the FILTER to reduce access to system bus. The filter makes every 4×4 sample block pipelined through the process units and achieves an efficiency of 80% for both the FILTER unit and the bus access unit. It can fulfill filtering process for a crystallographic information file （CIF, 352×288） format picture in 95 k clock cycles. The proposed design is part of a H.264/AVC decoder system-on-chip （SOC）, which is fabricated in 0.18 μm complementary metal oxide semiconductor （CMOS） process. The filter module consists of 60 k gates and 25.7 kb static random access memory （SRAM） and it can filter a macro-block in 240 clock cycles.
