A High Efficiency Hardware Implementation of S-Boxes Based on Composite Field for Advanced Encryption Standard

The SubBytes (S-box) transformation is the most crucial operation in the AES algorithm, significantly impacting the implementation performance of AES chips. To design a high-performance S-box, a segmented optimization implementation of the S-box is proposed based on the composite field inverse operation in this paper. This proposed S-box implementation is modeled using Verilog language and synthesized using Design Complier software under the premise of ensuring the correctness of the simulation result. The synthesis results show that, compared to several current S-box implementation schemes, the proposed implementation of the S-box significantly reduces the area overhead and critical path delay, then gets higher hardware efficiency. This provides strong support for realizing efficient and compact S-box ASIC designs.

Treatment and Hardware Removal after Lisfranc Injury: A Narrative Review

Lisfranc injuries can be difficult injuries to identify and treat, while also being the subject of significant debate on proper surgical management. A narrative literature review was performed using Pubmed and Google Scholar databases to identify recent studies evaluating open reduction internal fixation vs primary arthrodesis for Lisfranc injuries to further elucidate optimal surgical management. Additional focus was placed removal of hardware after ORIF to identify the need for routine hardware removal as an additional surgery may guide surgeon decision-making. This review showed inconclusive data on the superiority of ORIF vs arthrodesis, as multiple conflicting results exist, though established that functional results are similar between these options. Though both are generally accepted treatment options, there are no well-designed randomized controlled trials directly comparing the two. Retention of hardware after ORIF has been shown to be tolerated, though there is a significant risk of the need for unplanned removal due to pain and hardware breakage.

FPGA based hardware platform for trapped-ion-based multi-level quantum systems

We report a design and implementation of a field-programmable-gate-arrays(FPGA)based hardware platform,which is used to realize control and signal readout of trapped-ion-based multi-level quantum systems.This platform integrates a four-channel 2.8 Gsps@14 bits arbitrary waveform generator,a 16-channel 1 Gsps@14 bits direct-digital-synthesisbased radio-frequency generator,a 16-channel 8 ns resolution pulse generator,a 10-channel 16 bits digital-to-analogconverter module,and a 2-channel proportion integration differentiation controller.The hardware platform can be applied in the trapped-ion-based multi-level quantum systems,enabling quantum control of multi-level quantum system and highdimensional quantum simulation.The platform is scalable and more channels for control and signal readout can be implemented by utilizing more parallel duplications of the hardware.The hardware platform also has a bright future to be applied in scaled trapped-ion-based quantum systems.

Exploiting the Direct Link in IRS Assisted NOMA Networks with Hardware Impairments

Hardware impairments(HI)are always present in low-cost wireless devices.This paper investigates the outage behaviors of intelligent reflecting surface(IRS)assisted non-orthogonal multiple access(NOMA)networks by taking into account the impact of HI.Specifically,we derive the approximate and asymptotic expressions of the outage probability for the IRS-NOMA-HI networks.Based on the asymptotic results,the diversity orders under perfect self-interference cancellation and imperfect self-interference cancellation scenarios are obtained to evaluate the performance of the considered network.In addition,the system throughput of IRS-NOMA-HI is discussed in delay-limited mode.The obtained results are provided to verify the accuracy of the theoretical analyses and reveal that:1)The outage performance and system throughput for IRS-NOMA-HI outperforms that of the IRS-assisted orthogonal multiple access-HI(IRS-OMA-HI)networks;2)The number of IRS elements,the pass loss factors,the Rician factors,and the value of HI are pivotal to enhancing the performance of IRS-NOMAHI networks;and 3)It is recommended that effective methods of reducing HI should be used to ensure system performance,in addition to self-interference cancellation techniques.

List-Serial Pipelined Hardware Architecture for SCL Decoding of Polar Codes

For polar codes,the performance of successive cancellation list(SCL)decoding is capable of approaching that of maximum likelihood decoding.However,the existing hardware architectures for the SCL decoding suffer from high hardware complexity due to calculating L decoding paths simultaneously,which are unfriendly to the devices with limited logical resources,such as field programmable gate arrays(FPGAs).In this paper,we propose a list-serial pipelined hardware architecture with low complexity for the SCL decoding,where the serial calculation and the pipelined operation are elegantly combined to strike a balance between the complexity and the latency.Moreover,we employ only one successive cancellation(SC)decoder core without L×L crossbars,and reduce the number of inputs of the metric sorter from 2L to L+2.Finally,the FPGA implementations show that the hardware resource consumption is significantly reduced with negligible decoding performance loss.

System Outage Probability and Diversity Analysis of a SWIPT Based Two-Way DF Relay Network Under Transceiver Hardware Impairments

This paper investigates the system outage performance of a simultaneous wireless information and power transfer(SWIPT)based two-way decodeand-forward(DF)relay network,where potential hardware impairments(HIs)in all transceivers are considered.After harvesting energy and decoding messages simultaneously via a power splitting scheme,the energy-limited relay node forwards the decoded information to both terminals.Each terminal combines the signals from the direct and relaying links via selection combining.We derive the system outage probability under independent but non-identically distributed Nakagami-m fading channels.It reveals an overall system ceiling(OSC)effect,i.e.,the system falls in outage if the target rate exceeds an OSC threshold that is determined by the levels of HIs.Furthermore,we derive the diversity gain of the considered network.The result reveals that when the transmission rate is below the OSC threshold,the achieved diversity gain equals the sum of the shape parameter of the direct link and the smaller shape parameter of the terminalto-relay links;otherwise,the diversity gain is zero.This is different from the amplify-and-forward(AF)strategy,under which the relaying links have no contribution to the diversity gain.Simulation results validate the analytical results and reveal that compared with the AF strategy,the SWIPT based two-way relaying links under the DF strategy are more robust to HIs and achieve a lower system outage probability.

Temperature-Triggered Hardware Trojan Based Algebraic Fault Analysis of SKINNY-64-64 Lightweight Block Cipher

SKINNY-64-64 is a lightweight block cipher with a 64-bit block length and key length,and it is mainly used on the Internet of Things(IoT).Currently,faults can be injected into cryptographic devices by attackers in a variety of ways,but it is still difficult to achieve a precisely located fault attacks at a low cost,whereas a Hardware Trojan(HT)can realize this.Temperature,as a physical quantity incidental to the operation of a cryptographic device,is easily overlooked.In this paper,a temperature-triggered HT(THT)is designed,which,when activated,causes a specific bit of the intermediate state of the SKINNY-64-64 to be flipped.Further,in this paper,a THT-based algebraic fault analysis(THT-AFA)method is proposed.To demonstrate the effectiveness of the method,experiments on algebraic fault analysis(AFA)and THT-AFA have been carried out on SKINNY-64-64.In the THT-AFA for SKINNY-64-64,it is only required to activate the THT 3 times to obtain the master key with a 100%success rate,and the average time for the attack is 64.57 s.However,when performing AFA on this cipher,we provide a relation-ship between the number of different faults and the residual entropy of the key.In comparison,our proposed THT-AFA method has better performance in terms of attack efficiency.To the best of our knowledge,this is the first HT attack on SKINNY-64-64.

Secrecy Outage Probability for Two-Way Integrated Satellite Unmanned Aerial Vehicle Relay Networks with Hardware Impairments

In this paper,we investigate the secrecy outage performance for the two-way integrated satellite unmanned aerial vehicle relay networks with hardware impairments.Particularly,the closed-form expression for the secrecy outage probability is obtained.Moreover,to get more information on the secrecy outage probability in a high signalto-noise regime,the asymptotic analysis along with the secrecy diversity order and secrecy coding gain for the secrecy outage probability are also further obtained,which presents a fast method to evaluate the impact of system parameters and hardware impairments on the considered network.Finally,Monte Carlo simulation results are provided to show the efficiency of the theoretical analysis.

Hardware Security for IoT in the Quantum Era: Survey and Challenges

The Internet of Things (IoT) has become a reality: Healthcare, smart cities, intelligent manufacturing, e-agriculture, real-time traffic controls, environment monitoring, camera security systems, etc. are developing services that rely on an IoT infrastructure. Thus, ensuring the security of devices during operation and information exchange becomes a fundamental requirement inherent in providing safe and reliable IoT services. NIST requires hardware implementations that are protected against SCAs for the lightweight cryptography standardization process. These attacks are powerful and non-invasive and rely on observing the physical properties of IoT hardware devices to obtain secret information. In this paper, we present a survey of research on hardware security for the IoT. In addition, the challenges of IoT in the quantum era with the first results of the NIST standardization process for post-quantum cryptography are discussed.

Wavelet Denoising Applied to Hardware Redundant Systems for Rolling Element Bearing Fault Detection

This work presents a novel wavelet-based denoising technique for improving the signal-to-noise ratio(SNR)of nonsteady vibration signals in hardware redundant systems.The proposed method utilizes the relationship between redundant hardware components to effectively separate fault-related components from the vibration signature,thus enhancing fault detection accuracy.The study evaluates the proposed technique on two mechanically identical subsystems that are simultaneously controlled under the same speed and load inputs,with and without the proposed denoising step.The results demonstrate an increase in detection accuracy when incorporating the proposed denoising method into a fault detection system designed for hardware redundant machinery.This work is original in its application of a new method for improving performance when using residual analysis for fault detection in hardware redundant machinery configurations.Moreover,the proposed methodology is applicable to nonstationary equipment that experiences changes in both speed and load.

Spinal fusion-hardware construct: Basic concepts and imaging review

The interpretation of spinal images fixed with metallic hardware forms an increasing bulk of daily practice in a busy imaging department. Radiologists are required to be familiar with the instrumentation and operative options used in spinal fixation and fusion procedures, especially in his or her institute. This is critical in evaluating the position of implants and potential complications associated with the operative approaches and spinal fixation devices used. Thus, the radiologist can play an important role in patient care and outcome. This review outlines the advantages and disadvantages of commonly used imaging methods and reports on the best yield for each modality and how to overcome the problematic issues associated with the presence of metallic hardware during imaging. Baseline radiographs are essential as they are the baseline point for evaluation of future studies should patients develop symptoms suggesting possible complications. They may justify further imaging workup with computed tomography, magnetic resonance and/or nuclear medicine studies as the evaluation of a patient with a spinal implant involves a multi-modality approach. This review describes imaging features of potential complications associated with spinal fusion surgery as well as the instrumentation used. This basic knowledge aims to help radiologists approach everyday practice in clinical imaging.

Low-power emerging memristive designs towards secure hardware systems for applications in internet of things

Emerging memristive devices offer enormous advantages for applications such as non-volatile memories and inmemory computing(IMC),but there is a rising interest in using memristive technologies for security applications in the era of internet of things(IoT).In this review article,for achieving secure hardware systems in IoT,lowpower design techniques based on emerging memristive technology for hardware security primitives/systems are presented.By reviewing the state-of-the-art in three highlighted memristive application areas,i.e.memristive non-volatile memory,memristive reconfigurable logic computing and memristive artificial intelligent computing,their application-level impacts on the novel implementations of secret key generation,crypto functions and machine learning attacks are explored,respectively.For the low-power security applications in IoT,it is essential to understand how to best realize cryptographic circuitry using memristive circuitries,and to assess the implications of memristive crypto implementations on security and to develop novel computing paradigms that will enhance their security.This review article aims to help researchers to explore security solutions,to analyze new possible threats and to develop corresponding protections for the secure hardware systems based on low-cost memristive circuit designs.

Open-Source Hardware Is a Low-Cost Alternative for Scientific Instrumentation and Research

Scientific research requires the collection of data in order to study, monitor, analyze, describe, or understand a particular process or event. Data collection efforts are often a compromise: manual measurements can be time-consuming and labor-intensive, resulting in data being collected at a low frequency, while automating the data-collection process can reduce labor requirements and increase the frequency of measurements, but at the cost of added expense of electronic data-collecting instrumentation. Rapid advances in electronic technologies have resulted in a variety of new and inexpensive sensing, monitoring, and control capabilities which offer opportunities for implementation in agricultural and natural-resource research applications. An Open Source Hardware project called Arduino consists of a programmable microcontroller development platform, expansion capability through add-on boards, and a programming development environment for creating custom microcontroller software. All circuit-board and electronic component specifications, as well as the programming software, are open-source and freely available for anyone to use or modify. Inexpensive sensors and the Arduino development platform were used to develop several inexpensive, automated sensing and datalogging systems for use in agricultural and natural-resources related research projects. Systems were developed and implemented to monitor soil-moisture status of field crops for irrigation scheduling and crop-water use studies, to measure daily evaporation-pan water levels for quantifying evaporative demand, and to monitor environmental parameters under forested conditions. These studies demonstrate the usefulness of automated measurements, and offer guidance for other researchers in developing inexpensive sensing and monitoring systems to further their research.

THUBrachy:fast Monte Carlo dose calculation tool accelerated by heterogeneous hardware for high-dose-rate brachytherapy

The Monte Carlo(MC)simulation is regarded as the gold standard for dose calculation in brachytherapy,but it consumes a large amount of computing resources.The development of heterogeneous computing makes it possible to substantially accelerate calculations with hardware accelerators.Accordingly,this study develops a fast MC tool,called THUBrachy,which can be accelerated by several types of hardware accelerators.THUBrachy can simulate photons with energy less than 3 MeV and considers all photon interactions in the energy range.It was benchmarked against the American Association of Physicists in Medicine Task Group No.43 Report using a water phantom and validated with Geant4 using a clinical case.A performance test was conducted using the clinical case,showing that a multicore central processing unit,Intel Xeon Phi,and graphics processing unit(GPU)can efficiently accelerate the simulation.GPU-accelerated THUBrachy is the fastest version,which is 200 times faster than the serial version and approximately 500 times faster than Geant4.The proposed tool shows great potential for fast and accurate dose calculations in clinical applications.

Spectral Efficiency of Superimposed Pilots in Cell-Free Massive MIMO Systems with Hardware Impairments

In this paper,the spectral efficiency(SE)of an uplink hardware-constrained cell-free massive multi-input multi-output(MIMO)system with maximal ratio combining(MRC)receiver filters in the context of superimposed pilots(SPs)is investigated.Tractable closed-form SE expressions for the considered system are derived,which share us with opportunities to explore the impacts of the hardware quality coefficient,the length of coherence interval,and the power balance factor between pilot and data signals.Numerical results indicate that the achievable SE deteriorates as the hardware quality decreases and is more susceptible to the hardware impairments at the user equipments(UEs).Besides,we observe that SPs outperform regular pilots(RPs)in terms of SE and this performance gain is heavily dependent on the values of power balance factor and coherence interval.However,the superiorities of SPs over RPs have vanished when severe hardware imperfections are considered.

A Hardware Trojan Detection Method Based on the Electromagnetic Leakage

Hardware Trojan(HT) refers to a special module intentionally implanted into a chip or an electronic system. The module can be exploited by the attacker to achieve destructive functions. Unfortunately the HT is difficult to detecte due to its minimal resource occupation. In order to achieve an accurate detection with high efficiency, a HT detection method based on the electromagnetic leakage of the chip is proposed in this paper. At first, the dimensionality reduction and the feature extraction of the electromagnetic leakage signals in each group(template chip, Trojan-free chip and target chip) were realized by principal component analysis(PCA). Then, the Mahalanobis distances between the template group and the other groups were calculated. Finally, the differences between the Mahalanobis distances and the threshold were compared to determine whether the HT had been implanted into the target chip. In addition, the concept of the HT Detection Quality(HTDQ) was proposed to analyze and compare the performance of different detection methods. Our experiment results indicate that the accuracy of this detection method is 91.93%, and the time consumption is 0.042s in average, which shows a high HTDQ compared with three other methods.

System Verification of Hardware Optimization Based on Edge Detection

Nowadays, digital camera based remote controllers are widely used in people’s daily lives. It is known that the edge detection process plays an essential role in remote controlled applications. In this paper, a system verification platform of hardware optimization based on the edge detection is proposed. The Field-Programmable Gate Array (FPGA) validation is an important step in the Integrated Circuit (IC) design workflow. The Sobel edge detection algorithm is chosen and optimized through the FPGA verification platform. Hardware optimization techniques are used to create a high performance, low cost design. The Sobel edge detection operator is designed and mounted through the system Advanced High-performance Bus (AHB). Different FPGA boards are used for evaluation purposes. It is proved that with the proposed hardware optimization method, the hardware design of the Sobel edge detection operator can save 6% of on-chip resources for the Sobel core calculation and 42% for the whole frame calculation.

Hardware Performance Evaluation of SHA-3 Candidate Algorithms

Secure Hashing Algorithms (SHA) showed a significant importance in today’s information security applications. The National Institute of Standards and Technology (NIST), held a competition of three rounds to replace SHA1 and SHA2 with the new SHA-3, to ensure long term robustness of hash functions. In this paper, we present a comprehensive hardware evaluation for the final round SHA-3 candidates. The main goal of providing the hardware evaluation is to: find the best algorithm among them that will satisfy the new hashing algorithm standards defined by the NIST. This is based on a comparison made between each of the finalists in terms of security level, throughput, clock frequancey, area, power consumption, and the cost. We expect that the achived results of the comparisons will contribute in choosing the next hashing algorithm (SHA-3) that will support the security requirements of applications in todays ubiquitous and pervasive information infrastructure.

Hardware Implementation of STM32 Microcontroller-Based Indoor Environment Monitoring System

Microcontroller is widely used in the intelligent life of modern society. Intelligent development based on Microcontroller to solve the actual needs of people’s life, work, study and other fields is the core of Microcontroller application. Therefore, it is a task for researchers to understand the structure and performance of microcontroller, develop software, and be familiar with the method and process of intelligent development based on microcontroller. And with that in mind, this paper designs and produces a physical hardware system for indoor environment detection based on STM32 microcontroller. The system can detect the light intensity, temperature and humidity, and CO gas concentration in the indoor environment;and the data is integrated and processed by the STM32 microcontroller to display the current parameter values of each quantity in the indoor environment on a 3.5-inch resistive screen;at the same time, the PC can also log in to the OneNET cloud platform through the web page, and display the light intensity, temperature and humidity, and CO gas concentration values in the indoor environment in real time in the device created by OneNET for real-time viewing. The system can also display the light intensity, temperature and humidity, and CO gas concentration values in the indoor environment in real time. The hardware system has been tested and tested to achieve its function.

Design of Evolvable Hardware for Robotic Navigation

This paper presents an integrated on line learning system to evolve programmable logic array (PLA) controllers for navigating an autonomous robot in a two dimensional environment. The integrated on line learning system consists of two learning modules: one is the module of reinforcement learning based on temporal difference learning based on genetic algorithms, and the other is the module of evolutionary learning based on genetic algorithms. The control rules extracted from the module of reinforcement learning can be used as input to the module of evolutionary learning, and quickly implemented by the PLA through on line evolution. The on line evolution has shown promise as a method of learning systems in complex environment. The evolved PLA controllers can successfully navigate the robot to a target in the two dimensional environment while avoiding collisions with randomly positioned obstacles.