To achieve high parallel computation of discrete wavelet transform （DWT） in JPEG2000, a high-throughput two-dimensional （2D） 9/7 DWT very large scale integration （VLSI） design is proposed, in which the row proce...To achieve high parallel computation of discrete wavelet transform （DWT） in JPEG2000, a high-throughput two-dimensional （2D） 9/7 DWT very large scale integration （VLSI） design is proposed, in which the row processor is based on flipping structure. Due to the difference of the input data flow, the column processor is obtained by adding the input selector and data buffer to the row processor. Normalization steps in row and column DWT are combined to reduce the number of multipliers, and the rationality is verified. By rearranging the output of four-line row DWT with a multiplexer （MUX）, the amount of data processed by each column processor becomes half, and the four-input/four- output architecture is implemented. For an image with the size of N x N, the computing time of one-level 2D 9/7 DWT is 0.25N2 ＋ 1.5N clock cycles. The critical path delay is one multiplier delay, and only 5N internal memory is required. The results of post-route simulation on FPGA show that clock frequency reaches 136 MHz, and the throughput is 544 Msample/s, which satisfies the requirements of high-speed applications.展开更多
GE Senographe 2000D型数字乳腺X线钼靶机,在各大医院应用广泛。该型机一直由我院自己修理。本文描述了我遇到的两次故障和维修过程:首先利用工作站提供的错误信息和各种测试手段,判断故障大致方向,再加上长期以来维修的经验,最后找出...GE Senographe 2000D型数字乳腺X线钼靶机,在各大医院应用广泛。该型机一直由我院自己修理。本文描述了我遇到的两次故障和维修过程:首先利用工作站提供的错误信息和各种测试手段,判断故障大致方向,再加上长期以来维修的经验,最后找出故障点,从而顺利地解决了问题。展开更多
基金The National Science and Technology M ajor Project of the M inistry of Science and Technology of China(No.2014ZX03003007-009)
文摘To achieve high parallel computation of discrete wavelet transform （DWT） in JPEG2000, a high-throughput two-dimensional （2D） 9/7 DWT very large scale integration （VLSI） design is proposed, in which the row processor is based on flipping structure. Due to the difference of the input data flow, the column processor is obtained by adding the input selector and data buffer to the row processor. Normalization steps in row and column DWT are combined to reduce the number of multipliers, and the rationality is verified. By rearranging the output of four-line row DWT with a multiplexer （MUX）, the amount of data processed by each column processor becomes half, and the four-input/four- output architecture is implemented. For an image with the size of N x N, the computing time of one-level 2D 9/7 DWT is 0.25N2 ＋ 1.5N clock cycles. The critical path delay is one multiplier delay, and only 5N internal memory is required. The results of post-route simulation on FPGA show that clock frequency reaches 136 MHz, and the throughput is 544 Msample/s, which satisfies the requirements of high-speed applications.
