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A Study on Minimal Codewords in the Hamming Codes
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作者 Selda CALKAVUR 《Journal of Mathematics and System Science》 2013年第6期279-281,共3页
In this paper, we show that if Wmax 〈 6 for the Hamming code Ham (r, 2), then all of the nonzero codewords of Ham (r, 2) are minimal and if Wrnax 〈 8 for the extended Hamming code Hfim (r, 2), then all of the ... In this paper, we show that if Wmax 〈 6 for the Hamming code Ham (r, 2), then all of the nonzero codewords of Ham (r, 2) are minimal and if Wrnax 〈 8 for the extended Hamming code Hfim (r, 2), then all of the nonzero codewords ofHfim (r, 2) are minimal, where Wmax is the maximum nonzero weight in Ham (r, 2) and Hfim (r, 2). 展开更多
关键词 Linear code hamming code extended hamming code minimal codeword.
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Multiple bit upsets mitigation in memory by using improved hamming codes and parity codes 被引量:1
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作者 祝名 肖立伊 田欢 《Journal of Harbin Institute of Technology(New Series)》 EI CAS 2010年第5期726-730,共5页
This paper combines improved Hamming codes and parity codes to assure the reliability of memory in presence of multiple bit upsets with low cost overhead.The redundancy bits of improved Hamming codes will be appended ... This paper combines improved Hamming codes and parity codes to assure the reliability of memory in presence of multiple bit upsets with low cost overhead.The redundancy bits of improved Hamming codes will be appended at the end of data bits,which eliminates the overhead of interspersing the redundancy bits at the encoder and decoder.The reliability of memory is further enhanced by the layout architecture of redundancy bits and data bits.The proposed scheme has been implemented in Verilog and synthesized using the Synopsys tools.The results reveal that the proposed method has about 19% less area penalties and 13% less power consumption comparing with the current two-dimensional error codes,and its latency of encoder and decoder is 63% less than that of Hamming codes. 展开更多
关键词 MEMORY multiple bit upsets improved hamming codes two-dimensional error codes
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ERROR DETECTION CAPABILITY OF SHORTENED HAMMING CODES AND THEIR DUAL CODES
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作者 夏树涛 符方伟 《Acta Mathematicae Applicatae Sinica》 SCIE CSCD 2000年第3期292-298,共7页
The undetected error probability and error detection capability of shortened Hamming codes and their dual codes are studied in this paper. We also obtain some interesting properties for the shortened Simplex codes.
关键词 Error detection undetected error probability hamming codes simplex codes combinatorial codes
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Representations of Code Vertex Operator Superalgebras
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作者 Wei Jiang 《Algebra Colloquium》 SCIE CSCD 2015年第2期233-250,共18页
We study the representations of code vertex operator superalgebras resulting from a binary linear code which contains codewords of odd weight. We also show that there exists only one set of seven mutually orthogonal c... We study the representations of code vertex operator superalgebras resulting from a binary linear code which contains codewords of odd weight. We also show that there exists only one set of seven mutually orthogonal conformal vectors with central charge 1/2 in the Hamming code vertex operator superalgebra MH7. Phrthermore, we classify all the irreducible weak MH7-modules. 展开更多
关键词 vertex operator algebra irreducible module induced module code vertex operator superalgebra hamming code
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Implementation and verification of different ECC mitigation designs for BRAMs in flash-based FPGAs
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作者 杨振雷 王晓辉 +2 位作者 张战刚 刘杰 苏弘 《Chinese Physics C》 SCIE CAS CSCD 2016年第4期77-85,共9页
Embedded RAM blocks(BRAMs) in field programmable gate arrays(FPGAs) are susceptible to single event effects(SEEs) induced by environmental factors such as cosmic rays, heavy ions, alpha particles and so on. As t... Embedded RAM blocks(BRAMs) in field programmable gate arrays(FPGAs) are susceptible to single event effects(SEEs) induced by environmental factors such as cosmic rays, heavy ions, alpha particles and so on. As technology scales, the issue will be more serious. In order to tackle this issue, two different error correcting codes(ECCs), the shortened Hamming codes and shortened BCH codes, are investigated in this paper. The concrete design methods of the codes are presented. Also, the codes are both implemented in flash-based FPGAs. Finally, the synthesis report and simulation results are presented in the paper. Moreover, heavy-ion experiments are performed,and the experimental results indicate that the error cross-section of the device using the shortened Hamming codes can be reduced by two orders of magnitude compared with the device without mitigation, and no errors are discovered in the experiments for the device using the shortened BCH codes. 展开更多
关键词 codes mitigation correcting parity shortened programmable verification decoding hamming blocks
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