Cascaded ELM-Based Joint Frame Synchronization and Channel Estimation over Rician Fading Channel with Hardware Imperfections

Due to the interdependency of frame synchronization(FS)and channel estimation(CE),joint FS and CE(JFSCE)schemes are proposed to enhance their functionalities and therefore boost the overall performance of wireless communication systems.Although traditional JFSCE schemes alleviate the influence between FS and CE,they show deficiencies in dealing with hardware imperfection(HI)and deterministic line-of-sight(LOS)path.To tackle this challenge,we proposed a cascaded ELM-based JFSCE to alleviate the influence of HI in the scenario of the Rician fading channel.Specifically,the conventional JFSCE method is first employed to extract the initial features,and thus forms the non-Neural Network(NN)solutions for FS and CE,respectively.Then,the ELMbased networks,named FS-NET and CE-NET,are cascaded to capture the NN solutions of FS and CE.Simulation and analysis results show that,compared with the conventional JFSCE methods,the proposed cascaded ELM-based JFSCE significantly reduces the error probability of FS and the normalized mean square error(NMSE)of CE,even against the impacts of parameter variations.

A Novel Quantization and Model Compression Approach for Hardware Accelerators in Edge Computing

Massive computational complexity and memory requirement of artificial intelligence models impede their deploy-ability on edge computing devices of the Internet of Things(IoT).While Power-of-Two(PoT)quantization is pro-posed to improve the efficiency for edge inference of Deep Neural Networks(DNNs),existing PoT schemes require a huge amount of bit-wise manipulation and have large memory overhead,and their efficiency is bounded by the bottleneck of computation latency and memory footprint.To tackle this challenge,we present an efficient inference approach on the basis of PoT quantization and model compression.An integer-only scalar PoT quantization(IOS-PoT)is designed jointly with a distribution loss regularizer,wherein the regularizer minimizes quantization errors and training disturbances.Additionally,two-stage model compression is developed to effectively reduce memory requirement,and alleviate bandwidth usage in communications of networked heterogenous learning systems.The product look-up table(P-LUT)inference scheme is leveraged to replace bit-shifting with only indexing and addition operations for achieving low-latency computation and implementing efficient edge accelerators.Finally,comprehensive experiments on Residual Networks(ResNets)and efficient architectures with Canadian Institute for Advanced Research(CIFAR),ImageNet,and Real-world Affective Faces Database(RAF-DB)datasets,indicate that our approach achieves 2×∼10×improvement in the reduction of both weight size and computation cost in comparison to state-of-the-art methods.A P-LUT accelerator prototype is implemented on the Xilinx KV260 Field Programmable Gate Array(FPGA)platform for accelerating convolution operations,with performance results showing that P-LUT reduces memory footprint by 1.45×,achieves more than 3×power efficiency and 2×resource efficiency,compared to the conventional bit-shifting scheme.

V2I Physical Layer Security Beamforming with Antenna Hardware Impairments under RIS Assistance

The Internet of Vehicles(IoV)will carry a large amount of security and privacy-related data,which makes the secure communication between the IoV terminals increasingly critical.This paper studies the joint beamforming for physical-layer security transmission in the coexistence of Vehicle-to-Infrastructure(V2I)and Vehicle-toVehicle(V2V)communication with Reconfigurable Intelligent Surface(RIS)assistance,taking into account hardware impairments.A communication model for physical-layer security transmission is established when the eavesdropping user is present and the base station antenna has hardware impairments assisted by RIS.Based on this model,we propose to maximize the V2I physical-layer security transmission rate.To solve the coupled non-convex optimization problem,an alternating optimization algorithm based on second-order cone programming and semidefinite relaxation is proposed to obtain the optimal V2I base station transmit precoding and RIS reflect phase shift matrix.Finally,simulation results are presented to verify the convergence and superiority of our proposed algorithm while analyzing the impact of system parameters on the V2I physical-layer security transmission rate.The simulation results further demonstrate that the proposed robust beamforming algorithm considering hardware impairments will achieve an average performance improvement of 0.7 dB over a non-robustly designed algorithm.Furthermore,increasing the number of RIS reflective units from 10 to 50 results in an almost 2 dB enhancement in secure transmission rate.

A High Efficiency Hardware Implementation of S-Boxes Based on Composite Field for Advanced Encryption Standard

The SubBytes (S-box) transformation is the most crucial operation in the AES algorithm, significantly impacting the implementation performance of AES chips. To design a high-performance S-box, a segmented optimization implementation of the S-box is proposed based on the composite field inverse operation in this paper. This proposed S-box implementation is modeled using Verilog language and synthesized using Design Complier software under the premise of ensuring the correctness of the simulation result. The synthesis results show that, compared to several current S-box implementation schemes, the proposed implementation of the S-box significantly reduces the area overhead and critical path delay, then gets higher hardware efficiency. This provides strong support for realizing efficient and compact S-box ASIC designs.

Wavelet Denoising Applied to Hardware Redundant Systems for Rolling Element Bearing Fault Detection

This work presents a novel wavelet-based denoising technique for improving the signal-to-noise ratio(SNR)of nonsteady vibration signals in hardware redundant systems.The proposed method utilizes the relationship between redundant hardware components to effectively separate fault-related components from the vibration signature,thus enhancing fault detection accuracy.The study evaluates the proposed technique on two mechanically identical subsystems that are simultaneously controlled under the same speed and load inputs,with and without the proposed denoising step.The results demonstrate an increase in detection accuracy when incorporating the proposed denoising method into a fault detection system designed for hardware redundant machinery.This work is original in its application of a new method for improving performance when using residual analysis for fault detection in hardware redundant machinery configurations.Moreover,the proposed methodology is applicable to nonstationary equipment that experiences changes in both speed and load.

Treatment and Hardware Removal after Lisfranc Injury: A Narrative Review

Lisfranc injuries can be difficult injuries to identify and treat, while also being the subject of significant debate on proper surgical management. A narrative literature review was performed using Pubmed and Google Scholar databases to identify recent studies evaluating open reduction internal fixation vs primary arthrodesis for Lisfranc injuries to further elucidate optimal surgical management. Additional focus was placed removal of hardware after ORIF to identify the need for routine hardware removal as an additional surgery may guide surgeon decision-making. This review showed inconclusive data on the superiority of ORIF vs arthrodesis, as multiple conflicting results exist, though established that functional results are similar between these options. Though both are generally accepted treatment options, there are no well-designed randomized controlled trials directly comparing the two. Retention of hardware after ORIF has been shown to be tolerated, though there is a significant risk of the need for unplanned removal due to pain and hardware breakage.

FPGA based hardware platform for trapped-ion-based multi-level quantum systems

We report a design and implementation of a field-programmable-gate-arrays(FPGA)based hardware platform,which is used to realize control and signal readout of trapped-ion-based multi-level quantum systems.This platform integrates a four-channel 2.8 Gsps@14 bits arbitrary waveform generator,a 16-channel 1 Gsps@14 bits direct-digital-synthesisbased radio-frequency generator,a 16-channel 8 ns resolution pulse generator,a 10-channel 16 bits digital-to-analogconverter module,and a 2-channel proportion integration differentiation controller.The hardware platform can be applied in the trapped-ion-based multi-level quantum systems,enabling quantum control of multi-level quantum system and highdimensional quantum simulation.The platform is scalable and more channels for control and signal readout can be implemented by utilizing more parallel duplications of the hardware.The hardware platform also has a bright future to be applied in scaled trapped-ion-based quantum systems.

List-Serial Pipelined Hardware Architecture for SCL Decoding of Polar Codes

For polar codes,the performance of successive cancellation list(SCL)decoding is capable of approaching that of maximum likelihood decoding.However,the existing hardware architectures for the SCL decoding suffer from high hardware complexity due to calculating L decoding paths simultaneously,which are unfriendly to the devices with limited logical resources,such as field programmable gate arrays(FPGAs).In this paper,we propose a list-serial pipelined hardware architecture with low complexity for the SCL decoding,where the serial calculation and the pipelined operation are elegantly combined to strike a balance between the complexity and the latency.Moreover,we employ only one successive cancellation(SC)decoder core without L×L crossbars,and reduce the number of inputs of the metric sorter from 2L to L+2.Finally,the FPGA implementations show that the hardware resource consumption is significantly reduced with negligible decoding performance loss.

Exploiting the Direct Link in IRS Assisted NOMA Networks with Hardware Impairments

Hardware impairments(HI)are always present in low-cost wireless devices.This paper investigates the outage behaviors of intelligent reflecting surface(IRS)assisted non-orthogonal multiple access(NOMA)networks by taking into account the impact of HI.Specifically,we derive the approximate and asymptotic expressions of the outage probability for the IRS-NOMA-HI networks.Based on the asymptotic results,the diversity orders under perfect self-interference cancellation and imperfect self-interference cancellation scenarios are obtained to evaluate the performance of the considered network.In addition,the system throughput of IRS-NOMA-HI is discussed in delay-limited mode.The obtained results are provided to verify the accuracy of the theoretical analyses and reveal that:1)The outage performance and system throughput for IRS-NOMA-HI outperforms that of the IRS-assisted orthogonal multiple access-HI(IRS-OMA-HI)networks;2)The number of IRS elements,the pass loss factors,the Rician factors,and the value of HI are pivotal to enhancing the performance of IRS-NOMAHI networks;and 3)It is recommended that effective methods of reducing HI should be used to ensure system performance,in addition to self-interference cancellation techniques.

System Outage Probability and Diversity Analysis of a SWIPT Based Two-Way DF Relay Network Under Transceiver Hardware Impairments

This paper investigates the system outage performance of a simultaneous wireless information and power transfer(SWIPT)based two-way decodeand-forward(DF)relay network,where potential hardware impairments(HIs)in all transceivers are considered.After harvesting energy and decoding messages simultaneously via a power splitting scheme,the energy-limited relay node forwards the decoded information to both terminals.Each terminal combines the signals from the direct and relaying links via selection combining.We derive the system outage probability under independent but non-identically distributed Nakagami-m fading channels.It reveals an overall system ceiling(OSC)effect,i.e.,the system falls in outage if the target rate exceeds an OSC threshold that is determined by the levels of HIs.Furthermore,we derive the diversity gain of the considered network.The result reveals that when the transmission rate is below the OSC threshold,the achieved diversity gain equals the sum of the shape parameter of the direct link and the smaller shape parameter of the terminalto-relay links;otherwise,the diversity gain is zero.This is different from the amplify-and-forward(AF)strategy,under which the relaying links have no contribution to the diversity gain.Simulation results validate the analytical results and reveal that compared with the AF strategy,the SWIPT based two-way relaying links under the DF strategy are more robust to HIs and achieve a lower system outage probability.

Temperature-Triggered Hardware Trojan Based Algebraic Fault Analysis of SKINNY-64-64 Lightweight Block Cipher

SKINNY-64-64 is a lightweight block cipher with a 64-bit block length and key length,and it is mainly used on the Internet of Things(IoT).Currently,faults can be injected into cryptographic devices by attackers in a variety of ways,but it is still difficult to achieve a precisely located fault attacks at a low cost,whereas a Hardware Trojan(HT)can realize this.Temperature,as a physical quantity incidental to the operation of a cryptographic device,is easily overlooked.In this paper,a temperature-triggered HT(THT)is designed,which,when activated,causes a specific bit of the intermediate state of the SKINNY-64-64 to be flipped.Further,in this paper,a THT-based algebraic fault analysis(THT-AFA)method is proposed.To demonstrate the effectiveness of the method,experiments on algebraic fault analysis(AFA)and THT-AFA have been carried out on SKINNY-64-64.In the THT-AFA for SKINNY-64-64,it is only required to activate the THT 3 times to obtain the master key with a 100%success rate,and the average time for the attack is 64.57 s.However,when performing AFA on this cipher,we provide a relation-ship between the number of different faults and the residual entropy of the key.In comparison,our proposed THT-AFA method has better performance in terms of attack efficiency.To the best of our knowledge,this is the first HT attack on SKINNY-64-64.

Hardware Security for IoT in the Quantum Era: Survey and Challenges

The Internet of Things (IoT) has become a reality: Healthcare, smart cities, intelligent manufacturing, e-agriculture, real-time traffic controls, environment monitoring, camera security systems, etc. are developing services that rely on an IoT infrastructure. Thus, ensuring the security of devices during operation and information exchange becomes a fundamental requirement inherent in providing safe and reliable IoT services. NIST requires hardware implementations that are protected against SCAs for the lightweight cryptography standardization process. These attacks are powerful and non-invasive and rely on observing the physical properties of IoT hardware devices to obtain secret information. In this paper, we present a survey of research on hardware security for the IoT. In addition, the challenges of IoT in the quantum era with the first results of the NIST standardization process for post-quantum cryptography are discussed.

Secrecy Outage Probability for Two-Way Integrated Satellite Unmanned Aerial Vehicle Relay Networks with Hardware Impairments

In this paper,we investigate the secrecy outage performance for the two-way integrated satellite unmanned aerial vehicle relay networks with hardware impairments.Particularly,the closed-form expression for the secrecy outage probability is obtained.Moreover,to get more information on the secrecy outage probability in a high signalto-noise regime,the asymptotic analysis along with the secrecy diversity order and secrecy coding gain for the secrecy outage probability are also further obtained,which presents a fast method to evaluate the impact of system parameters and hardware impairments on the considered network.Finally,Monte Carlo simulation results are provided to show the efficiency of the theoretical analysis.

Realization of nonlinear PID with feed-forward controller for 3-DOF flight simulator and hardware-in-the-loop simulation

As friction, intrinsic steady-state nonlinearity poses a challenging dilemma to the control system of 3-DOF （three degree of freedom） flight simulator, a novel hybrid control strategy of nonlinear PID （proportionalintegral-derivative） with additional FFC （feed-forward controller） is proposed, and the hardware-in-the-loop simulation results are also given. Based on the description of 3-DOF flight simulator, a novel nonlinear PID theory is well introduced. Then a nonlinear PID controller with additional FFC is designed. Subsequently, the loop structure of 3-DOF flight simulator is also designed. Finally, a series of hardware-in-the-loop simulation experiments are undertaken to verify the feasibility and effectiveness of the proposed nonlinear PID controller with additional FFC for 3-DOF flight simulator.

SPACECRAFT DOCKING SIMULATION USING HARDWARE-IN-THE-LOOP SIMULATOR WITH STEWART PLATFORM

A ground-based hardware-in-the-loop （HIL） simulation system with hydraulically driven Stewart platform for spacecraft docking simulation is presented. The system is used for simulating docking process of the on-orbit spacecraft. Principle and structure of the six-degree-of-freedom simulation system are introduced. The docking process dynamic of the vehicles is modeled. Experiment results and mathematical simulation data are compared to validating the simulation system. The comparisons of the results prove that the simulation system proposed can effectively simulate the on-orbit docking process of the spacecraft.

Development of a Low-cost Hardware-in-the-loop Simulation System as a Test Bench for Anti-lock Braking System

Nowadays validation of anti-lock braking systems（ABS） relies mainly on a large amount of road tests.An alternative means with higher efficiency is employing the hardware-in-the-loop simulation（HILS） system to substitute part of road tests for designing,testing,and tuning electronic control units（ECUs） of ABS.Most HILS systems for ABS use expensive digital signal processor hardware and special purpose software,and some fail-safe functions with regard to wheel speeds cannot be evaluated since artificial wheel speed signals are usually provided.In this paper,a low-cost ABS HILS test bench is developed and used for validating the anti-lock braking performance and tuning control parameters of ABS controllers.Another important merit of the proposed test bench is that it can comprehensively evaluate the fail-safe functions with regard to wheel speed signals since real tone rings and sensors are integrated in the bench.A 5-DOF vehicle model with consideration of longitudinal load transfer is used to calculate tire forces,wheel speeds and vehicle speed.Each of the four real-time wheel speed signal generators consists of a servo motor plus a ring gear,which has sufficient dynamic response ability to emulate the rapid changes of the wheel speeds under strict braking conditions of very slippery roads.The simulation of braking tests under different road adhesion coefficients using the HILS test bench is run,and results show that it can evaluate the anti-lock braking performance of ABS and partly the fail-safe functions.This HILS system can also be used in such applications as durability test,benchmarking and comparison between different ECUs.The test bench developed not only has a relatively low cost,but also can be used to validate the wheel speed-related ECU design and all its fail-safe functions,and a rapid testing and proving platform with a high efficiency for research and development of the automotive ABS is therefore provided.

Multi-dimensional and complicated electromagnetic interference hardware-in-the-loop simulation method

A typical electronic communication system, such as GPS receiver, unmanned aerial vehicle＇s （UAV＇s） data link, and radar, faces multi-dimensional and complicated electromagnetic interference in operating environment. To measure the anti- interference performance of the electronic communication system in the complicated electromagnetic interference environment, a method of multi-dimensional and complicated electromagnetic interference hardware-in-the-loop simulation in an anechoic room is proposed. It takes into account the characteristics of interference signals and the positional relationship among interference, the receiver and the transmitter of the electronic communication system. It uses the grey relational method and the angular domain mapping error correction method to control the relevant parameters, the microwave switch and so on, thus achieving the approximately actual mapping of the outdoor multi-dimensional and complicated electromagnetic interference in the anechoic room. To verify the effectiveness of this method, the multi-dimensional and complicated electromagnetic interference of the UAV＇s data link is simulated as an example. The results show that the degree of correlation between the calculated signal to interference ratio of the data link receiver in the actual scene and the measured signal to interference ratio of the data link receiver simulated with this method in the anechoic room is 0.968 1, proving that the method is effective for simulating the complicated electromagnetic interference.

Hardware-in-the-Loop Research on the Electronic Control Unit for Diesel Engines

A hardware-in-the-loop simulating platform is developed to avoid designing defects caused by the complicated logical structure and multiple-functional buildup of the dectronic control unit（ECU）in modem diesel engines, and to diminish potential damages on components or human exposure to dangers in R＆D en- deavor. This plat-form consists of a computer installed with software Matlab/Simulink/RTW and dSPACE/ ControlDesk; a diesel engine ECU, and a dSPACE autobox which runs a real-time diesel engine model. A typical model of diesel engine with turbocharger and intercooler is presented. Based on this model our research is carried out with a real ECU to test its software control strategies. Results show that by using the diesel engine model downloaded inside, the hardware-in-the-loop platform can simulate diesel engine＇s working conditions and generate all kinds of sensor signals which ECU needs on a real-time basis. So the ECU control strategies can be validated and relevant parameters roughly calibrated.

Hardware-in-the-loop simulation of communication networks

To enhance the fidelity and accuracy of the simulation of communication networks,hardware-in-the-loop（HITL） simulation was employed.HITL simulation methods was classified into three categories,of which the merits and shortages were compared.Combing system-in-the-loop（SITL） simulation principle with high level architecture（HLA）,an HITL simulation model of asynchronous transfer mode（ATM） network was constructed.The throughput and end-to-end delay of all-digital simulation and HITL simulation was analyzed,which showed that HITL simulation was more reliable and effectively improved the simulation credibility of communication network.Meanwhile,HLA-SITL method was fast and easy to achieve and low-cost during design lifecycle.Thus,it was a feasible way to research and analyze the large-scale network.

New Solution on Distributed Hardware-in-the-Loop Radar System Simulation on HLA

In the large-scale distributed hardware-in-the-loop radar simulation system based on HLA, a new solution of processing after acquisition is proposed, which separates the software subsystem from the hardware jammer subsystem by a response database, so as to settle the problem, that the software subsystem can not meet the real-time need of the hardware, with very little increment of code. And the data completeness and feasibility of this solution are discussed.