SiC gate-controlled bipolar field effect composite transistor with polysilicon region for improving on-state current

A novel silicon carbide gate-controlled bipolar field effect composite transistor with poly silicon region(SiC GCBTP)is proposed.Different from the traditional electrode connection mode of SiC vertical diffused MOS(VDMOS),the P+region of P-well is connected with the gate in SiC GCBTP,and the polysilicon region is added between the P+region and the gate.By this method,additional minority carriers can be injected into the drift region at on-state,and the distribution of minority carriers in the drift region will be optimized,so the on-state current is increased.In terms of static characteristics,it has the same high breakdown voltage(811 V)as SiC VDMOS whose length of drift is 5.5μm.The on-state current of SiC GCBTP is 2.47×10^(-3)A/μm(V_(G)=10 V,V_(D)=10 V)which is 5.7 times of that of SiC IGBT and 36.4 times of that of SiC VDMOS.In terms of dynamic characteristics,the turn-on time of SiC GCBTP is only 0.425 ns.And the turn-off time of SiC GCBTP is similar to that of SIC insulated gate bipolar transistor(IGBT),which is 114.72 ns.

Temperature dependence of single-event transients in SiGe heterojunction bipolar transistors for cryogenic applications

We experimentally demonstrate that the dominant mechanism of single-event transients in silicon-germanium heterojunction bipolar transistors(SiGe HBTs)can change with decreasing temperature from+20℃to-180℃.This is accomplished by using a new well-designed cryogenic experimental system suitable for a pulsed-laser platform.Firstly,when the temperature drops from+20℃to-140℃,the increased carrier mobility drives a slight increase in transient amplitude.However,as the temperature decreases further below-140℃,the carrier freeze-out brings about an inflection point,which means the transient amplitude will decrease at cryogenic temperatures.To better understand this result,we analytically calculate the ionization rates of various dopants at different temperatures based on Altermatt's new incomplete ionization model.The parasitic resistivities with temperature on the charge-collection pathway are extracted by a two-dimensional(2D)TCAD process simulation.In addition,we investigate the impact of temperature on the novel electron-injection process from emitter to base under different bias conditions.The increase of the emitter-base junction's barrier height at low temperatures could suppress this electron-injection phenomenon.We have also optimized the built-in voltage equations of a high current compact model(HICUM)by introducing the impact of incomplete ionization.The present results and methods could provide a new reference for effective evaluation of single-event effects in bipolar transistors and circuits at cryogenic temperatures,and could provide a new evidence of the potential of SiGe technology in applications in extreme cryogenic environments.

High performance carrier stored trench bipolar transistor with dual shielding structure

We propose a novel high performance carrier stored trench bipolar transistor(CSTBT)with dual shielding structure(DSS-CSTBT).The proposed DSS-CSTBT features a double trench structure with different trench profiles in the surface,in which a shallow gate trench is shielded by a deep emitter trench and a thick oxide layer under it.Compared with the conventional CSTBT(con-CSTBT),the proposed DSS-CSTBT not only alleviates the negative impact of the shallow gate trench and highly doped CS layer on the breakdown voltage(BV),but also well reduces the gate-collector capacitance CGC,gate charge Q_(G),and turn-off loss E_(OFF)of the device.Furthermore,lower turn-on loss E_(ON)and gate drive loss E_(DR)are also obtained.Simulation results show that with the same CS layer doping concentration N_(CS)=1.5×10^(16)cm^(-3),the BV increases from 1312 V of the con-CSTBT to 1423 V of the proposed DSS-CSTBT with oxide layer thickness under gate(T_(og2))of 1μm.Moreover,compared with the con-CSTBT,the C_(GC)at V_(CE)of 25 V and miller plateau charge(Q_(GC))for the proposed DSS-CSTBT with T_(og2)of 1μm are reduced by 79.4%and 74.3%,respectively.With the VGEincreases from 0 V to 15 V,the total QGfor the proposed DSS-CSTBT with T_(og2)of 1μm is reduced by 49.5%.As a result,at the same on-state voltage drop(V_(CEON))of 1.55 V,the E_(ON)and E_(OFF)are reduced from 20.3 mJ/cm^(2)and 19.3 mJ/cm^(2)for the con-CSTBT to8.2 mJ/cm^(2)and 9.7 mJ/cm^(2)for the proposed DSS-CSTBT with T_(og2)of 1μm,respectively.The proposed DSS-CSTBT not only significantly improves the trade-off relationship between the V_(CEON)and E_(OFF)but also greatly reduces the E_(ON).

Sensitivity study of the SiGe heterojunction bipolar transistor single event effect based on pulsed laser and technology computer-aided design simulation

The single event effect of a silicon–germanium heterojunction bipolar transistor(SiGe HBT) was thoroughly investigated. By considering the worst bias condition, the sensitive area of the proposed device was scanned with a pulsed laser.With variation of the collector bias and pulsed laser incident energy, the single event transient of the SiGe HBT was studied.Moreover, the single event transient produced by laser irradiation at a wavelength of 532 nm was more pronounced than at a wavelength of 1064 nm. Finally, the impact of the equivalent linear energy transfer of the 1064 nm pulsed laser on the single event transient was qualitatively examined by performing technology computer-aided design simulations, and a good consistency between the experimental data and the simulated outcomes was attained.

Numerical Simulation and Analysis of Bipolar Junction Photogate Transistor for CMOS Image Sensor

A new photodetector--bipolar junction photogate transistor is presented for CMOS image sensor and its analytical model is also established.With the technical parameter of the 0.6μm CMOS process,the bipolar junction photogate transistor is analyzed and simulated.The simulated results illustrate that the bipolar junction photogate transistor has the similar characteristics of the traditional photogate transistor.The photocurrent density of the bipolar junction photogate transistor increases exponentially with the incidence light power due to introducing the injection p+n junction.Its characteristic of blue response is rather improved compared to the traditional photogate transistor that benefits to increase the color photograph made up of the red,the green,and the blue.

The Bipolar Field-Effect Transistor:Ⅰ.Electrochemical Current Theory(Two-MOS-Gates on Pure-Base)

This paper describes the bipolar field-effect transistor （BiFET） and its theory. Analytical solution is ob- tained from partitioning the two-dimensional transistor into two one-dimensional transistors. The analysis employs the parametric surface-electric-potential and the electrochemical （quasi-Fermi） potential-gradient driving force to compute the current. Output and transfer D. C. current and conductance versus voltage are presented over practi- cal ranges of terminal D. C. voltages and device parameters. Electron and hole surface channel currents are pres- ent simultaneously, a new feature which could provide circuit functions in one physical transistor such as the CMOS inverter and SRAM memory.

The Bipolar Theory of the Field-Effect Transistor:X.The Fundamental Physics and Theory(All Device Structures)

This paper describes the foundation underlying the device physics and theory of the semiconductor field effect transistor which is applicable to any devices with two carrier species in an electric field. The importance of the boundary conditions on the device current-voltage characteristics is discussed. An illustration is given of the transfer DCIV characteristics computed for two boundary conditions,one on electrical potential,giving much higher drift-limited parabolic current through the intrinsic transistor, and the other on the electrochemical potentials, giving much lower injection-over-thebarrier diffusion-limited current with ideal 60mV per decade exponential subthreshold roll-off, simulating electron and hole contacts. The two-MOS-gates on thin pure-body silicon field-effect transistor is used as examples

The Bipolar Field-Effect Transistor: III.Short Channel Electrochemical Current Theory (Two-MOS-Gates on Pure-Base)

This paper describes the short channel theory of the bipolar field-effect transistor （BiFET） by partitioning the transistor into two sections,the source and drain sections,each can operate as the electron or hole emitter or collector under specific combinations of applied terminal voltages. Analytical solution is obtained in the source and drain sections by separating the two-dimensional trap-free Shockley Equations into two one-dimensional equations parametrically coupled via the surface-electric-potential and by using electron current continuity and hole current continuity at the boundary between the emitter and collector sections. Total and electron-hole-channel components of the output and transfer currents and conductances, and the electrical lengths of the two sections are computed and presented in graphs as a function of the D. C. terminal voltages for the model transistor with two identical and connected metal-oxide-silicon-gates （MOS-gates） on a thin pure-silicon base over practical ranges of thicknesses of the silicon base and gate oxide. Deviations of the long physical channel currents and conductances from those of the short electrical channels are reported.

The Bipolar Field-Effect Transistor:Ⅳ.Short Channel Drift-Diffusion Current Theory(Two-MOS-Gates on Pure-Base)

This paper gives the short channel analytical theory of the bipolar field-effect transistor （BiFET） with the drift and diffusion currents separately computed in the analytical theory. As in the last-month paper which represented the drift and diffusion current by the single electrochemical （potential-gradient） current, the two-dimensional transistor is partitioned into two sections, the source and drain sections, each can operate as the electron or hole emitter or collector under specific combinations of applied terminal voltages. Analytical solution is then obtained in the source and drain sections by separating the two-dimensional trap-free Shockley Equations into two one-dimensional equations parametrically coupled via the surface-electric-potential and by using electron current continuity and hole current continuity at the boundary between the emitter and collector sections. Total and the drift and diffusion components of the electron-channel and hole-channel currents and output and transfer conductances, and the electrical lengths of the two sections are computed and presented in graphs as a function of the D. C. terminal voltages for the model transistor with two identical and connected metal-oxide-silicon-gates （MOS-gates） on a thin pure-silicon base over practical ranges of thicknesses of the silicon base and gate oxide. Deviations of the two-section short-channel theory from the one-section long-channel theory are described.

The Theory of Field-Effect Transistors:XI. The Bipolar Electrochemical Currents(1-2-MOS-Gates on Thin-Thick Pure-Impure Base)

The field-effect transistor is inherently bipolar, having simultaneously electron and hole surface and volume channels and currents. The channels and currents are controlled by one or more externally applied transverse electric fields. It has been known as the unipolar field-effect transistor for 55-years since Shockley＇s 1952 invention,because the electron-current theory inevitably neglected the hole current from over-specified internal and boundary conditions, such as the electrical neutrality and the constant hole-electrochemical-potential, resulting in erroneous solutions of the internal and terminal electrical characteristics from the electron channel current alone, which are in gross error when the neglected hole current becomes comparable to the electron current, both in subthreshold and strong inversion. This report presents the general theory, that includes both electron and hole channels and currents. The rectangular （ x, y, z） parallelepiped transistors,uniform in the width direction （z-axis）,with one or two MOS gates on thin and thick,and pure and impure base, are used to illustrate the two-dimensional effects and the correct internal and boundary conditions for the electric and the electron and hole electrochemical potentials. Complete analytical equations of the DC current-voltage characteristics of four common MOS transistor structures are derived without over-specification： the 1-gate on semi-infinite-thick impure-base （the traditional bulk transistor）, the 1-gate on thin impure-silicon layer over oxide-insulated silicon bulk （SOI） ,the 1-gate on thin impure-silicon layer deposited on insulating glass （SOI TFT）, and the 2-gates on thin pure-base （FinFETs）.

'The Theory of Field-Effect Transistors XII.The Bipolar Drift and Diffusion Currents(1-2-MOS-Gates on Thin-Thick Pure-Impure Base)

The previous report （XI） gave the electrochemical-potential theory of the Bipolar Field-Effect Transistors. This report （XII） gives the drift-diffusion theory. Both treat 1-gate and 2-gate, pure-base and impure-base, and thin and thick base. Both utilize the surface and bulk potentials as the parametric variables to couple the voltage and current equations. In the present drift-diffusion theory, the very many current terms are identified by their mobility multiplier for the components of drift current,and the diffusivity multiplier for the components of the diffusion current. Complete analytical driftdiffusion equations are presented to give the DC current-voltage characteristics of four common MOS transistor structures. The drift current consists of four terms： 1-D （One-Dimensional） bulk charge drift term, 1-D carrier space-charge drift term,l-D Ex^2 （transverse electric field） drift term,2-D drift term. The diffusion current consists of three terms： 1-D bulk charge diffusion term,l-D carrier space-charge diffusion term,and 2-D diffusion term. The 1-D Ex^2 drift term was missed by all the existing transistor theories, and contributes significantly, as much as 25 % of the total current when the base layer is nearly pure. The 2-D terms come from longitudinal gradient of the longitudinal electric field,which scales as the square of the Debye to Channel length ratio, at 25nm channel length with nearly pure base, （LD/L）^2 = 10^6 but with impurity concentration of 10^18cm^-3 , （LD/L）^2 = 10^-2 .

The Bipolar Field-Effect Transistor:V.Bipolar Electrochemical Current Theory(Two-MOS-Gates on Thin-Base)

This paper reports the intrinsic-structure DC characteristics computed from the analytical electrochemical current theory of the bipolar field-effect transistor （BiFET） with two identical MOS gates on nanometer-thick pure-base of silicon with no generation-recombination-trapping. Numerical solutions are rapidly obtained for the three potential variables,electrostatic and electron and hole electrochemical potentials,to give the electron and hole surface and volume channel currents,using our cross-link two-route or zig-zag one-route recursive iteration algorithms. Boundary conditions on the three potentials dominantly affect the intrinsic-structure DC characteristics,illustrated by examples covering 20-decades of current （10-22 to 10-2 A/Square at 400cm^2/（V · s） mobility for 1.5nm gate-oxide, and 30nm-thick pure-base）. Aside from the domination of carrier space-charge-limited drift current in the strong surface channels,observed in the theory is also the classical drift current saturation due to physical pinch-off of an impure-base volume channel depicted by the 1952 Shockley junction-gate field-effect transistor theory,and its extension to complete cut-off of the pure-base volume channel,due to vanishing carrier screening by the few electron and hole carriers in the pure-base,with Debye length （25mm） much larger than device dimension （25nm）.

The Bipolar Field-Effect Transistor:II.Drift-Diffusion Current Theory(Two-MOS-Gates on Pure-Base)

This paper describes the drift-diffusion theory of the bipolar field-effect transistor （BiFET） with two identical and connected metal-oxide-silicon-gates （MOS-gates） on a thin-pure-base. Analytical solution is obtained by partitioning the two-dimensional transistor into two one-dimensional problems coupled by the parametric sur- face-electric-potential. Total and component output and transfer currents and conductances versus D. C. voltages from the drift-diffusion theory, and their deviations from the electrochemical （quasi-Fermi） potential-gradient theory,are presented over practical ranges of thicknesses of the silicon base and gate oxide. A substantial contri- bution from the longitudinal gradient of the square of the transverse electric field is shown.

Microwave damage susceptibility trend of a bipolar transistor as a function of frequency

We conduct a theoretical study of the damage susceptibility trend of a typical bipolar transistor induced by a high-power microwave （HPM） as a function of frequency. The dependences of the burnout time and the damage power on the signal frequency are obtained. Studies of the internal damage process and the mechanism of the device are carried out from the variation analysis of the distribution of the electric field, current density, and temperature. The investigation shows that the burnout time linearly depends on the signal frequency. The current density and the electric field at the damage position decrease with increasing frequency. Meanwhile, the temperature elevation occurs in the area between the p-n junction and the n n＋ interface due to the increase of the electric field. Adopting the data analysis software, the relationship between the damage power and frequency is obtained. Moreover, the thickness of the substrate has a significant effect on the burnout time.

Novel lateral insulated gate bipolar transistor on SOI substrate for optimizing hot-carrier degradation

A novel lateral insulated gate bipolar transistor on a silicon-on-insulator substrate SOI-LIGBT with a special low-doped P-well structure is proposed.The P-well structure is added to attach the P-body under the channel so as to reduce the linear anode current degradation without additional process.The influence of the length and depth of the P-well on the hot-carrier HC reliability of the SOI-LIGBT is studied.With the increase in the length of the P-well the perpendicular electric field peak and the impact ionization peak diminish resulting in the reduction of the hot-carrier degradation. In addition the impact ionization will be weakened with the increase in the depth of the P-well which also makes the hot-carrier degradation decrease.Considering the effect of the low-doped P-well and the process windows the length and depth of the P-well are both chosen as 2 μm.

Analysis of displacement damage effects on bipolar transistors irradiated by spallation neutrons

Displacement damage induced by neutron irradiation in China Spallation Neutron Source(CSNS) is studied on bipolar transistors with lateral PNP, substrate PNP, and vertical NPN configurations, respectively. Comparison of the effects on different type transistors is conducted based on displacement damage factor, and the differences are analyzed through minority carrier lifetime calculation and structure analysis. The influence of CSNS neutrons irradiation on the lateral PNP transistors is analyzed by the gate-controlled method, including the oxide charge accumulation, surface recombine velocity,and minority carrier lifetime. The results indicate that the total ionizing dose in CSNS neutron radiation environment is negligible in this study. The displacement damage factors based on 1-MeV equivalent neutron flux of different transistors are consistent between Xi’an pulse reactor(XAPR) and CSNS.

A novel high-voltage light punch-through carrier stored trench bipolar transistor with buried p-layer

A novel high-voltage light punch-through（LPT） carrier stored trench bipolar transistor（CSTBT） with buried p-layer（BP） is proposed in this paper.Since the negative charges in the BP layer modulate the bulk electric field distribution,the electric field peaks both at the junction of the p base/n-type carrier stored（N-CS） layer and the corners of the trench gates are reduced,and new electric field peaks appear at the junction of the BP layer/N drift region.As a result,the overall electric field in the N drift region is enhanced and the proposed structure improves the breakdown voltage（BV） significantly compared with the LPT CSTBT.Furthermore,the proposed structure breaks the limitation of the doping concentration of the N-CS layer（NN CS） to the BV,and hence a higher NN CS can be used for the proposed LPT BP-CSTBT structure and a lower on-state voltage drop（Vce（sat）） can be obtained with almost constant BV.The results show that with a BP layer doping concentration of NBP = 7 × 10^15 cm^-3,a thickness of LBP = 2.5 μm,and a width of WBP = 5 μm,the BV of the proposed LPT BP-CSTBT increases from 1859 V to 1862 V,with NN CS increasing from 5 × 10^15 cm^-3 to 2.5 × 10^16 cm^-3.However,with the same N-drift region thickness of 150 μm and NN CS,the BV of the CSTBT decreases from 1598 V to 247 V.Meanwhile,the Vce（sat） of the proposed LPT BP-CSTBT structure decreases from 1.78 V to 1.45 V with NN CS increasing from 5 × 10^15 cm^-3 to 2.5 × 10^16 cm^-3.

Hardening measures for bipolar transistors against microwave-induced damage

In the present paper we study the influences of the bias voltage and the external components on the damage progress of a bipolar transistor induced by high-power microwaves. The mechanism is presented by analyzing the variation in the internal distribution of the temperature in the device. The findings show that the device becomes less vulnerable to damage with an increase in bias voltage. Both the series diode at the base and the relatively low series resistance at the emitter, Re, can obviously prolong the burnout time of the device. However, Re will aid damage to the device when the value is sufficiently high due to the fact that the highest hot spot shifts from the base-emitter junction to the base region. Moreover, the series resistance at the base Rb will weaken the capability of the device to withstand microwave damage.

Effects of microwave pulse-width damage on a bipolar transistor

This paper presents a theoretical study of the pulse-width effects on the damage process of a typical bipolar transistor caused by high power microwaves（HPMs） through the injection approach.The dependences of the microwave damage power,P,and the absorbed energy,E,required to cause the device failure on the pulse width τ are obtained in the nanosecond region by utilizing the curve fitting method.A comparison of the microwave pulse damage data and the existing dc pulse damage data for the same transistor is carried out.By means of a two-dimensional simulator,ISE-TCAD,the internal damage processes of the device caused by microwave voltage signals and dc pulse voltage signals are analyzed comparatively.The simulation results suggest that the temperature-rising positions of the device induced by the microwaves in the negative and positive half periods are different,while only one hot spot exists under the injection of dc pulses.The results demonstrate that the microwave damage power threshold and the absorbed energy must exceed the dc pulse power threshold and the absorbed energy,respectively.The dc pulse damage data may be useful as a lower bound for microwave pulse damage data.

Two-dimensional analysis of the interface state effect on current gain for a 4H-SiC bipolar junction transistor

This paper studies two-dimensional analysis of the surface state effect on current gain for a 4H-SiC bipolar junction transistor （BJT）. Simulation results indicate the mechanism of current gain degradation, which is surface Fermi level pinning leading to a strong downward bending of the energy bands to form the channel of surface electron recombination current. The experimental results are well-matched with the simulation, which is modeled by exponential distributions of the interface state density replacing the single interface state trap. Furthermore, the simulation reveals that the oxide quality of the base emitter junction interface is very important for 4H-SiC BJT performance.