A High Linearity,13bit Pipelined CMOS ADC

A 13bit,pipelined analog-to-digital converter （ADC） designed to achieve high linearity is described. The high linearity is realized by using the passive capacitor error-averaging technique to calibrate the capacitor mismatch error, a gain-boosting opamp to minimize the finite gain error and gain nonlinearity,a bootstrapping switch to reduce the switch on-resistor nonlinearity, and an anti-disturb design to reduce the noise from the digital supply. This ADC is implemented in 0.18μm CMOS technology and occupies a die area of 3.2mm^2 , including pads. Measured performance includes - 0.18/ 0.15LSB of differential nonlinearity, -0.35/0.5LSB of integral nonlinearity, 75.7dB of signal-to-noise plus distortion ratio （SNDR） and 90. 5 dBc of spurious-free dynamic range （SFDR） for 2.4MHz input at 2.5MS/s. At full speed conversion （5MS/s） and for the same 2.4MHz input, the measured SNDR and SFDR are 73.7dB and 83.9 dBc, respectively. The power dissipation including output pad drivers is 21mW at 2.5MS/s and 34mW at 5MS/s,both at 2.7V supply.

A High Linearity CMOS DVB-S Front-End

A direct conversion CMOS DVB-S front-end employs a T-configuration variable attenuator,a single-to- differential low noise amplifier, and a low noise mixer. By innovative use of the attenuator, the linearity handling ability of the system is dramatically improved. The system is designed and fabricated in SMIC 0.18 μm RF CMOS technology. The measurement data show that the front-end provides a total of more than 30rib dynamic range and a noise figure of 5dB in the wide frequency signal band. The prototype front-end consumes only 10mA and achieves an IIP3 of ＋ 20dBm.

Design of a combined magnetic negative stiffness mechanism with high linearity in a wide working region

Combining magnetic negative stiffness mechanism(NSM) in parallel with positive stiffness has been considered to be an effective approach to realize the quasi-zero stiffness(QZS) characteristic,thus resolving the contradiction between high load capacity and(ultra-) low-frequency vibration isolation capability.However,the remarkable stiffness nonlinearity of common magnetic NSMs restricts the displacement region with reliable negative stiffness,resulting in considerable nonlinear behavior,poor vibration attenuation performance,and probable instability under large amplitude vibrations.A novel combined negative stiffness mechanism(CNSM) with attractive magnetic NSM(ANSM) and repulsive magnetic NSM(RNSM) in parallel is proposed in this paper.The stiffness nonlinearities of the ANSM and RNSM in the CNSM are counteracted through the parallel configuration such that the displacement region with reliable linear stiffness of the CNSM is widened by several times.An analytical model of the CNSM is established by the magnetic charge model and verified by simulation on ANSYS Maxwell.Parametric studies are then conducted to investigate the effects of design parameters on the stiffness characteristic,providing guidelines for the optimal design of the CNSM.Meanwhile,the stiffness and nonlinearity of the CNSM are compared with that of a single ANSM and RNSM.Static and dynamic experiments are finally conducted on the proposed test prototypes.Experimental results demonstrated the validity of the established model and the effectiveness of the CNSM in generating high linear stiffness within a wide displacement region and lowering the resonance frequency.Thus,the proposed CNSM can be applied in(ultra-) low-frequency vibration isolation under large amplitude excitations.

A high linearity SiGe HBT LNA for GPS receiver

A high linearity 1.575 GHz SiGe：HBT low noise amplifier （LNA） for global positioning system applications is described. The bipolar cascoded with an MOSFET LNA was fabricated in a commercial 0.18 μm SiGe BiCMOS process, A resistor bias feed circuit with a feedback resistor was designed for the LNA input transistor to improve its intermodulation and compression performance. The packaged chip tested on board has displayed a noise figure of 1. I 1 dB, a power gain of 18 dB, an output 1 dB compression point of ＋7.8 dBm and an input third-order intercept point of ＋1.8 dBm. The chip occupies a 500 × 560μm^2 area and consumes 3.6 mA from a 2.85 V power supply.

A high linearity multi-band and gain adjustable channel-select filter for TV-tuner application

This paper presents a channel-select filter that employs an active-RC bi-quad structure for TV-tuner application. A design method to optimize the IIP3 of the bi-quad is developed. Multi-band selection and gain adjustment are implemented using switching resistors in the resistor array and capacitors in the capacitor array. Q-factor degradation is compensated by a tuning segmented resistor. A feed-forward OTA with high gain and low third-order distortion is applied in the bi-quad to maximize linearity performance and minimize area by avoiding extra compensation capacitor use. An RC tuning circuit and DC offset cancellation circuit are designed to overcome the process variation and DC offset, respectively. The experimental results yield an in-band IIP3 of more than 31 dBm at 0 dB gain, a 54 dB gain range with 6 dB gain step, and a continuous frequency tuning range from 0.25 to 4 MHz. The in-band ripple is less than 1.4 dB at high gain mode, while the gain error and frequency tuning error are no more than 3.4% and 5%, respectively. The design, which is fabricated in a 0.18 μm CMOS process, consumes 12.6 mW power at a 1.8 V supply and occupies 1.28 mm2.

A 50 MHz-1 GHz high linearity CATV amplifier with a 0.15μm InGaAs PHEMT process

A 50 MHz-1 GHz low noise and high linearity amplifier monolithic-microwave integrated-circuit （MMIC） for cable TV is presented.A shunt AC voltage negative feedback combined with source current negative feedback is adopted to extend the bandwidth and linearity.A novel DC bias feedback is introduced to stabilize the operation point,which improved the linearity further.The circuit was fabricated with a 0.15μm InGaAs PHEMT （pseudomorphic high electron mobility transistor） process.The test was carried out in 75Ωsystems from 50 MHz to 1 GHz.The measurement results showed that it gave a small signal gain of 16.5 dB with little gain ripples of less than±1dB.An excellent noise figure of 1.7-2.9 dB is obtained in the designed band.The IIP3 is 16 dBm, which shows very good linearity.The CSO and CTB are high up to 68 dBc and 77 dBc,respectively.The chip area is 0.56 mm^2 and the power dissipation is 110 mA with a 5 V supply.It is ideally suited to cable TV systems.

High linearity current communicating passive mixer employing a simple resistor bias

A high linearity current communicating passive mixer including the mixing cell and transimpedance amplifier(TIA) is introduced.It employs the resistor in the TIA to reduce the source voltage and the gate voltage of the mixing cell.The optimum linearity and the maximum symmetric switching operation are obtained at the same time.The mixer is implemented in a 0.25μm CMOS process.The test shows that it achieves an input third-order intercept point of 13.32 dBm,conversion gain of 5.52 dB,and a single sideband noise figure of 20 dB.

A wideband large dynamic range and high linearity RF front-end for U-band mobile DTV

A wideband large dynamic range and high linearity U-band RF front-end for mobile DTV is introduced, and includes a noise-cancelling low-noise amplifier （LNA）, an RF programmable gain amplifier （RFPGA） and a current communicating passive mixer. The noise/distortion cancelling structure and RC post-distortion compensation are employed to improve the linearity of the LNA. An RFPGA with five stages provides large dynamic range and fine gain resolution. A simple resistor voltage network in the passive mixer decreases the gate bias voltage of the mixing transistor, and optimum linearity and symmetrical mixing is obtained at the same time. The RF front-end is implemented in a 0.25 #m CMOS process. Tests show that it achieves an IIP3 （third-order intercept point） of -17 dBm, a conversion gain of 39 dB, and a noise figure of 5.8 dB. The RFPGA achieves a dynamic range of-36.2 to 23.5 dB with a resolution of 0.32 dB.

A high linearity current mode multiplier/divider with a wide dynamic range

A high linearity current mode multiplier/divider （CMM/D） with a wide dynamic range is presented. The proposed CMM/D is based on the voltage-current characteristic of the diode, thus wide dynamic range is achieved. In addition, high linearity is achieved because high accuracy current mirrors are adopted and the output current is insensitive to the temperature and device parameters of the fabrication process. Furthermore, no extra bias current for all input signals is required and thus power saving is realized. With proper selection of establishing the input terminal, the proposed circuit can perform as a mulfifunction circuit to he operated as a multiplier/divider, without changing its topology. The proposed circuit is implemented in a 0.25μm BCD process and the chip area is 0.26 ~ 0.24 mm2. The simulation and measurement results show that the maximum static linearity error is 4-1.8% and the total harmonic distortion is 0.4% while the input current ranges from 0 to 200 μA.

A 2.5 mW 370 mV/pF high linearity stray-immune symmetrical readout circuit for capacitive sensors

A stray-insensitive symmetrical capacitance-to-voltage converter for capacitive sensors is presented. By introducing a reference branch,a symmetrical readout circuit is realized.The linear input range is increased, and the systematic offsets of two input op-amps are cancelled.The common-mode noise and even-order distortion are also rejected.A chopper stabilization technique is adopted to further reduce the offset and flicker noise of the op-amps,and a Verilog-A-based varactor is used to model the real variable sensing capacitor.Simulation results show that the output voltage of this proposed readout circuit responds correctly,while the under-test capacitance changes with a frequency of 1 kHz.A metal-insulator-metal capacitor array is designed on chip for measurement, and the measurement results show that this circuit achieves sensitivity of 370 mV/pF,linearity error below 1%and power consumption as low as 2.5 mW.This symmetrical readout circuit can respond to an FPGA controlled sensing capacitor array changed every 1 ms.

Influence of High-Speed Milling Process on Mechanical and Microstructural Properties of Ultrafine Grained Profiles Produced by Linear Flow Splitting

The effects of milling parameters on the surface quality,microstructures and mechanical properties of machined parts with ultrafine grained(UFG)gradient microstructures are investigated.The effects of the cutting speed,feed per tooth,cutting tool geometry and cooling strategy are demonstrated.It has been found that the surface quality of machined grooves can be improved by increasing the cutting speed.However,cryogenic cooling with CO_2 exhibits no significant improvement of surface quality.Microstructure and hardness investigations revealed similar microstructure and hardness variations near the machined groove walls for both utilized tool geometries.Therefore,cryogenic cooling can decrease more far-ranging hardness reductions due to high process temperatures,especially in the UFG regions of the machined parts,whilst it cannot prevent the drop in hardness directly at the groove walls.

HIGH PERFORMANCE SPARSE SOLVER FOR UNSYMMETRICAL LINEAR EQUATIONS WITH OUT-OF-CORE STRATEGIES AND ITS APPLICATION ON MESHLESS METHODS

A new direct method for solving unsymmetrical sparse linear systems（USLS） arising from meshless methods was introduced. Computation of certain meshless methods such as meshless local Petrov-Galerkin （MLPG） method need to solve large USLS. The proposed solution method for unsymmetrical case performs factorization processes symmetrically on the upper and lower triangular portion of matrix, which differs from previous work based on general unsymmetrical process, and attains higher performance. It is shown that the solution algorithm for USLS can be simply derived from the existing approaches for the symmetrical case. The new matrix factorization algorithm in our method can be implemented easily by modifying a standard JKI symmetrical matrix factorization code. Multi-blocked out-of-core strategies were also developed to expand the solution scale. The approach convincingly increases the speed of the solution process, which is demonstrated with the numerical tests.

A HIGH VELOCITY FEED UNIT DRIVEN BY LINEAR MOTOR

In order to realize high speed machining, the special requirements for feed transmission system of the CNC machine tool have to be satisfied. A high velocity feed unit driven by a induction linear motor is developed. The compositions of the high velocity CNC feed unit and main problems in the unit design are discussed.

Development of High-Thrust and Double-Sided Linear Synchronous Motor Module For Liquid Crystal Display Equipment

Recently,there is an increasing requirement for controlling linear motion up to a few hundred of millimeter strokes in the area of the liquid crystal display(LCD) production equipment.The requirements of the motion system for LCD production equipment are high acceleration and high velocity with positioning accuracy.To satisfy these requirements,it has to be designed with the high-thrust force and low velocity ripple.In this work, high-thrust and double-sided linear synchronous motor (LSM)module is proposed and the developed high-thrust and double-sided LSM module is verified by performance test.

Study on a New High Frequency Moving Coil Permanent Magnet Linear Motor

In order to improve the characteristics of a conventional moving coil permanent magnet linear motor （MCPMLM）, such as weak points on export force, response time, response speed, we studied a permanent magnet （PM） structure that is a key component of MCPMLM. Different magnetization techniques of single PM and differ- ent array structures of multiple PMs are compared, and a new MCPMLM magnetized along the external field force lines wing eight pieces of a tegular Halbach magnet array with air gaps is proposed as well. The analysis on magnetic field and experimental results of MCPMLM demonstrates that the force between the coil and the PM increases by more than 40%. The simulation frequeney is close to 350 Hz at -3 dB , and the response time is O. 005 s. In addition, the experiment frequency reaches 300 Hz at -3 dB and the response time is 0. 004 s, which agrees well with the simulation results. It means that the developed MCPMLM enjoys advantages in high frequency and rapid response, and can satisfy the requirements of a high speed electro-hydraulic proportional valve.

Unified parametric approaches for high-order integral observer design for matrix second-order linear systems

A type of high-order integral observers for matrix second-order linear systems is proposed on the basis of generalized eigenstructure assignment via unified parametric approaches. Through establishing two general parametric solutions to this type of generalized matrix second-order Sylvester matrix equations, two unified complete parametric methods for the proposed observer design problem are presented. Both methods give simple complete parametric expressions for the observer gain matrices. The first one mainly depends on a series of singular value decompositions, and is thus numerically simple and reliable; the second one utilizes the fight factorization of the system, and allows eigenvalues of the error system to be set undetermined and sought via certain optimization procedures. A spring-mass-dashpot system is utilized to illustrate the design procedure and show the effect of the proposed approach.

NON-LINEAR CRITICAL LAYER IN EL NINO AND LA NINA YEARS AND FORMATION, MAINTENTENANCE AND OSCILLATION OF THE SUBTROPICAL HIGH

Monthly mean zonal wind data from the European Center for Medium-range Weather Forecasting(ECMWF) t'or December 1982, April 1983, October 1984 and ApriI 1985 are used in numerical integration as thebasic flow in a non-linear critical-layer model. The subtropical high is extensive and limited in number if simulated with the basic now in December 1982 and April 1983. It consists of 2 to 3 cells that move westward at alloscillatory periods of 1~ 2 months. The subtropical high, simulated with the basic flow in October 1984 and April1 985. is weak and small in coverage, or distributed in strips that contain up to 4 cells. The high. merged or spillover a short time. is moving westward. The years 1982 ~ 1983 are a process of EI Nino while the years 1984- 1985one of La Nina. lt is known from the chart of energy flux that it oscillates by a much larger amplitude and longerperiod in the El Nino year than in the La Nina year. All the results above have indicated that the basic now' in theEl Nino year is enhancing the subtropical high lagging by about 4 months and that in the La Nina year is decay'ing it. It is consiStent with the well-known observational fact that the SSTA in the equatorial eastern Pacitlc ispositively correlated with the extent and intensity of the subtropical high in west Pacific lagging by 1 ~2 seasons.The result is also important for further study of the formation, maintenance and oscillation of the subtropicalhigh.

NON-LINEAR DYNAMIC MODEL RETRIEVAL OF SUBTROPICAL HIGH BASED ON EMPIRICAL ORTHOGONAL FUNCTION AND GENETIC ALGORITHM

Aiming at the difficulty of accurately constructing the dynamic model of subtropical high, based on the potential height field time series over 500 hPa layer of T106 numerical forecast products, by using EOF（empirical orthogonal function） temporal-spatial separation technique, the disassembled EOF time coefficients series were regarded as dynamical model variables, and dynamic system retrieval idea as well as genetic algorithm were introduced to make dynamical model parameters optimization search, then, a reasonable non-linear dynamic model of EOF time-coefficients was established. By dynamic model integral and EOF temporal-spatial components assembly, a mid-/long-term forecast of subtropical high was carried out. The experimental results show that the forecast results of dynamic model are superior to that of general numerical model forecast results. A new modeling idea and forecast technique is presented for diagnosing and forecasting such complicated weathers as subtropical high.

A CMOS high-IF down-conversion mixer for WLAN 802.11a applications

A low noise, high conversion gain down-conversion mixer for WLAN 802.11a applications, which adopts the high intermediate frequency （IF） topology, is presented. The input radio frequency （RF）band, local oscillator（LO）frequency band and output IF are 5.15 to 5.35, 4.15 to 4.35 and 1 GHz, respectively. Source resistive degeneration technique and pseudo-differential Gilbert topology are used to achieve high linearity, and, current bleeding technique and LC resonant loads are used to acquire a low noise figure. In addition, the mixer adopts a common-source transistor pair cross-stacked with a source follow pair（CSSF）circuit as an output buffer to enhance the mixer＇s conversion gain but not deteriorate the other performances. The mixer is implemented in 0.18 μm RF CMOS（complementary metal oxide semiconductor transistor）technology and the chip area of the mixer including all bonding pads is 580 μm×1 185 μm. The measured results show that under a 1.8 V supply, the conversion gain is 10.1 dB; the input 1 dB compression point and the input-referred third-order intercept point are-3.5 and 5.3 dBm, respectively; the single side band （SSB）noise figure （NF）is 8.65 dB, and the core current consumption is 3.8 mA.

具有优异汉明相关特性的混沌跳频序列构造方法

跳频通信具有码分多址、频带共享、抗干扰和抗截获的能力,在无线通信系统中得到了广泛的应用。目前基于混沌方法构造的跳频序列大多具有较高的线性复杂度,所得到的跳频序列虽然具有良好的随机性,但是其汉明相关性还不够。在选取具有优异汉明相关特性的m序列的基础上,结合混沌序列,利用笛卡尔积构造得到了具有优异汉明自相关性的跳频序列。该跳频序列具备与混沌序列一致的线性复杂度,而且可以保证其周期不小于m序列的周期,汉明自相关值不超过m序列的汉明自相关值。